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Substrate structure and packaging member provided with the same

A package and substrate technology, which is applied to electrical components, electrical solid-state devices, semiconductor devices, etc., can solve the problems that the package substrate 20 cannot pass the reliability test, peeling, etc., and achieve the effect of improving the overall yield.

Active Publication Date: 2014-02-12
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the edge position A where the semiconductor chip 21 projects onto the copper layer 201 in the flip chip scale package (FCCSP) has a relatively large stress. layer 201 peeling off, resulting in the failure of the entire package substrate 20 to pass the reliability test

Method used

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  • Substrate structure and packaging member provided with the same
  • Substrate structure and packaging member provided with the same
  • Substrate structure and packaging member provided with the same

Examples

Experimental program
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no. 1 example

[0034] image 3 What is shown is a cross-sectional view of the first embodiment of the substrate structure and package of the present invention. It first provides a substrate structure, the substrate structure includes: substrate body 30, its material can be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide) , PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy resin glass fiber (Glass fiber); metal layer 31, which is formed on a surface 30a of the substrate body 30; an insulating protective layer 32 (such as solder resist green paint), which is formed on the surface 30a of the substrate body 30, and has an opening 320 exposing the metal layer 31; And a crystal placement area 300, which is defined on the surface 30a of the substrate body 30, for connecting a semiconductor chip 33 on the surface 30a, wherein, a said crystal placement ...

no. 2 example

[0040] Figure 4 What is shown is a cross-sectional view of the second embodiment of the substrate structure and package of the present invention. It first provides a substrate structure, which includes: a substrate body 30; a metal layer 31 formed on a surface 30a of the substrate body 30; an insulating protective layer 32 formed on the surface 30a of the substrate body 30 , and has an opening 320 exposing the metal layer 31; and a crystal placement area 300, which is defined on the surface 30a of the substrate body 30, for placing a semiconductor chip 33 on the surface 30a, wherein the metal layer 31 is not Beyond the range of the crystal placement region 300 , and the crystal placement region 300 is preferably located in the center of the opening 320 .

[0041]The package of the present embodiment connects the semiconductor chip 33 at the die placement region 300 of the aforementioned substrate structure, so that the semiconductor chip 33 is located in the center of the op...

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PUM

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Abstract

The invention provides a substrate structure and a packaging member provided with the same. The substrate structure comprises a substrate body, a metal layer, an insulation protection layer, and a wafer carrying area. The metal is disposed on one surface of the substrate body, and the insulation protection layer is disposed on the surface of the substrate body, and is provided with an opening used for exposing the metal layer. The wafer carrying area is disposed on the surface of the substrate body, and is sued for carrying a semiconductor chip disposed on the surface. The wafer carrying area is corresponding to the opening, and the range of the wafer carrying area comprises the whole opening, or the metal layer does not exceed the scope of the wafer carrying area. The invention is advantageous in that the delaminating phenomenon of the packaging member can be reduced, and the yield can be increased.

Description

technical field [0001] The present invention relates to a substrate structure and package, especially to a substrate structure and package for flip-chip packaging. Background technique [0002] Typical flip-chip packages include flip-chip ball grid array (FCBGA) packages (such as figure 1 As shown) and flip chip chip scale package (FCCSP), the difference between the two is that the packaging substrate of the flip chip ball grid array (FCBGA) package is larger and thicker, so it is more rigid. It is mostly used in the bearing and electrical connection of the central processing unit (CPU) and the graphics processing unit (GPU). Usually, the manufacturing method of the flip-chip ball grid array (FCBGA) package first connects the semiconductor chip 11 to the packaging substrate 10. , and between the semiconductor chip 11 and the packaging substrate 10 is filled with a capillary underfill (CUF) technology to protect the solder balls 13 and expose the non-active surface 111 of th...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L23/31
CPCH01L2224/16225H01L2224/32225H01L2224/73204H01L2924/00
Inventor 洪良易邱士超萧惟中白裕呈
Owner SILICONWARE PRECISION IND CO LTD