Wiring substrate with embedded semiconductor and built-in positioning parts and its manufacturing method

Abstract

The invention relates to a wiring substrate with embedded semiconductors, built-in positioning components, and double build-up circuits, and a manufacturing method thereof. According to a preferred implementation aspect of the present invention, the method includes: forming a positioning element on a dielectric layer; using the positioning element as a disposition guide for a semiconductor element to arrange the semiconductor element on the dielectric layer; attaching a reinforcement layer on the dielectric layer; forming a first build-up circuit and a second build-up circuit covering the semiconductor element, the positioning member, and the reinforcement layer on both sides; providing a covered through hole, the A coated via provides an electrical connection between the first build-up circuit and the second build-up circuit. Accordingly, the positioning member can accurately limit the disposition position of the semiconductor element, and avoid electrical connection failure between the semiconductor and the build-up circuit.

Description

technical field [0001] The invention relates to a wiring substrate for semiconductor components and its manufacturing method, especially a wiring substrate with embedded semiconductors and built-in positioning parts, and its manufacturing method. Background technique [0002] The market trend of electronic devices requires thinner, smarter, and cheaper portable electronic devices. The semiconductor components used in these electronic devices need to further reduce their size and improve their electronic performance at a lower cost . Among the various tried methods, the module formed by embedding or building semiconductor chips in the printed circuit board is considered to be the most efficient method, which can greatly reduce the overall weight, thickness, and shorten the distance through the internal connection This enables improved electronic performance. [0003] However, trying to embed chips in circuit boards encounters many problems. For example, embedded chips can c...

AI Technical Summary

Problems solved by technology

[0003] However, trying to embed chips in circuit boards encounters many problems. For example, embedded chips can cause chips to be horizontal and vertical due to the thermal properties of the plastic material during attachment and packaging / lamination processes. displacement

Coefficient of thermal expansion (CTE) mismatches between metals, dielectrics, and silicon at various thermal processing stages will lead to dislocation of built-in interconnect structures disposed thereon

U.S. Patent No. 7,935,893 of Tanaka et al.; U.S. Patent No. 7,944,039 of Aral; and U.S. Patent No. 7,405,103 of Chang disclosed various alignment methods for solving the production yield, but none of them proposed can provide an appropriate Or an effective method to control the displacement of the chip, which causes the originally attached chip to be misaligned in the predetermined setting position due to the reflow of the adhesive under the chip when it is cured, even when using highly accurate alignment marks and equipment. produces the same problem

Chino's U.S. Patent Application No. 2010 / 0184256 discloses a resin sealing method to fix semiconductor elements to an adhesive layer formed on a support, which is effective in controlling the chip from further displacement during the sealing process. However, this method does not Provides the control or adjustment of any chip attachment process, and the dislocation of the chip caused by the reflow of the adhesive used to attach the chip is unavoidable

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