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Composite circuit boards with built-in spacers, interposers, and build-up circuits

A composite circuit and positioning technology, which is applied to circuits, printed circuit parts, electrical components, etc., can solve the problems of inability to set low-K value semiconductor chips, composite circuit boards prone to bending, and laser beams aligning with contact pads, etc. Achieve the effect of being suitable for mass manufacturing, improving product yield and low price

Inactive Publication Date: 2016-06-15
BRIDGE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the composite circuit board has an asymmetric structure and the thermal expansion coefficient of the interposer is different from that of the build-up circuit, the composite circuit board is prone to bending, resulting in the situation that the interposer cannot be equipped with a low-K value semiconductor chip
In addition, when the interposer needs to be placed on the circuit before the highly precise conductive blind vias forming the internal connections, if the placement accuracy of the interposer is uncertain, or the die adhesive under the interposer is cured would "re-flow", it would be impossible to align the laser beam on the contact pads, thus, possibly resulting in degradation of yield or reliability

Method used

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  • Composite circuit boards with built-in spacers, interposers, and build-up circuits
  • Composite circuit boards with built-in spacers, interposers, and build-up circuits
  • Composite circuit boards with built-in spacers, interposers, and build-up circuits

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] Figure 1A and 1B is a cross-sectional view of a method for forming a spacer on a dielectric layer in an embodiment of the present invention, and Figure 1C for Figure 1B top view.

[0035] Figure 1A It is a cross-sectional view of a laminated structure including a metal layer 11 , a dielectric layer 21 , and a support plate 23 . The metal layer 11 shown in the figure is a copper layer with a thickness of 50 microns, however, the metal layer 11 can also be various metal materials, and is not limited to the copper layer. In addition, the metal layer 11 can be deposited on the dielectric layer 21 by various techniques, including lamination, electroplating, electroless plating, evaporation, sputtering, and combinations thereof to deposit a single-layer or multi-layer structure, and its The thickness is preferably in the range of 10 to 200 microns.

[0036] The dielectric layer 21 is generally made of epoxy resin, glass epoxy resin, polyimide, and the like, and has a ...

Embodiment 2

[0062] Figures 6A-6D According to another embodiment of the present invention, it is a cross-sectional view of a method for preparing a composite circuit board with electrically connected first wires and a reinforcing layer. For the purpose of brevity, any statement in Example 1 may be incorporated into the same application section here, and the same statement will not be repeated.

[0063] Figure 6A Cross-sectional view of the structure prepared by the steps of Figure 1A3A.

[0064] Figure 6B A cross-sectional view of the structure for thinning the support plate 23 to form the metal layer 24 with a desired thickness. The metal layer 24 shown in the figure is a copper layer with a thickness of about 15 microns, and the dielectric layer 21 is considered as the first dielectric layer 211 of the build-up circuit.

[0065] Figure 6C It is a cross-sectional view of the structure of the first blind hole 213 formed through the first dielectric layer 211 and the adhesive 131 ...

Embodiment 3

[0070] Figure 7A and 7B are respectively a cross-sectional view and a top view of a composite circuit board 103 according to yet another embodiment of the present invention, and the composite circuit board 103 has a configuration guide 115 near the peripheral edge of the reinforcement layer 41 .

[0071] In this embodiment, the composite circuit board 103 is made by the method shown in Embodiment 1, except that when the selected part of the metal layer 11 is removed and the positioning member 113 is formed, the positioning member 115 is formed at the same time, so as to accurately The setting position of the reinforcing layer 41 is defined. The configuration guide 115 extends upward from the first dielectric layer 211 beyond the attachment surface of the reinforcement layer 41 , and is directionally aligned with the four outer surfaces of the reinforcement layer 41 , and extends beyond the surface of the reinforcement layer 41 in the lateral direction. Four outer surfaces. ...

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PUM

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Abstract

A hybrid wiring board includes an interposer, a stopper, a stiffener and a build-up circuitry. The stopper is laterally aligned with and laterally extends beyond peripheral edges of the interposer in lateral directions. The interposer extends into an aperture of the stiffener and is electrically connected to the build-up circuitry. The build-up circuitry covers the stopper, the interposer and the stiffener and provides signal routing for the interposer. The stiffener provides mechanical supports, ground / power planes and heat sinks for the build-up circuitry.

Description

technical field [0001] The invention relates to a composite circuit board, in particular to a composite circuit board with a built-in positioning element, which includes an intermediate layer, a positioning element, a strengthening layer, and a build-up circuit. Background technique [0002] The traditional flip-chip package includes a flipped semiconductor chip, and is connected to a laminated substrate through an array of solder bumps. Generally speaking, the spacing of the matching contact pads on the laminated substrate is shorter than that of the backside contact pads. Fine, so that the laminated substrate can accommodate chips with high I / O value, and the packaged assembly can be easily attached to the printed circuit board of the next layer of assembly. In order to meet finer functions and higher performance requirements, modern semiconductor chips use dielectric materials with low K values ​​as interlayer materials. When the low-K dielectric material is porous, frag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H05K1/02H01L23/498
CPCH01L24/19H01L2224/16225H01L2224/16227H01L2224/19H01L2224/45144H01L2924/00H01L2924/00012
Inventor 林文强王家忠
Owner BRIDGE SEMICON