Semiconductor component with dual connection channels between interposer and coreless substrate

A coreless substrate, semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., to achieve the effects of high reliability, cost reduction, and high reliability

Inactive Publication Date: 2016-12-28
BRIDGE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the solder used to connect the silicon interposer to the package substrate may have reliability issues, although resin material is used to fill its interface to strengthen its structure

Method used

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  • Semiconductor component with dual connection channels between interposer and coreless substrate
  • Semiconductor component with dual connection channels between interposer and coreless substrate
  • Semiconductor component with dual connection channels between interposer and coreless substrate

Examples

Experimental program
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Effect test

Embodiment 1

[0045] Figures 1A-1J According to an implementation aspect of the present invention, a method for manufacturing a semiconductor component, the semiconductor component includes an interposer, a semiconductor chip, a reinforcement layer, and a coreless substrate, and the coreless substrate is connected through wire bonding and conductive micro-holes. electrically connected to the interposer.

[0046] Such as Figure 1JAs shown, the semiconductor component 110 includes an interposer 31 , a strengthening layer 41 , a semiconductor chip 51 , a coreless substrate 20 , and wire bonding 321 . The interposer 31 includes a first surface 311 , a second surface 313 opposite to the first surface 311 , a first contact pad 312 and bonding fingers 316 on the first surface 311 , and a second contact pad 314 on the second surface 313 , the conductive via 318 partially connected to the first contact pad 312 and the second contact pad 314 , and the lateral circuit 320 electrically connected to ...

Embodiment 2

[0066] figure 2 Another three-dimensional device 310 according to another embodiment of the present invention has an additional first conductive microhole 243 in direct contact with the interposer 41 for grounding or electrical connection with passive components. figure 2 The sealing material 71 and the heat sink 81 are also shown in . The sealing material 71 (such as molding compound) fills the via hole 411 in an upward direction and covers the connection pad 111 , the spacer 113 , the first dielectric layer 21 , and the interposer 31 . A heat sink 81 (such as copper or aluminum) is attached to the reinforcement layer 41 and the semiconductor chip 51 via a thermally conductive adhesive 801 to assist heat dissipation, and the heat sink 81 covers the reinforcement layer 41 , the sealing material 71 , and the semiconductor chip 51 in an upward direction.

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PUM

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Abstract

The invention relates to a semiconductor component with double connection channels between the interposer and the coreless substrate. The semiconductor component includes a semiconductor element, an intermediate layer with a through hole, a coreless substrate, and a strengthening layer. The semiconductor element is flip-chip on the intermediary layer, and the intermediary layer is fixed on the coreless substrate through an adhesive, and extends into a through hole of a reinforcement layer, and the reinforcement layer provides mechanical support for the coreless substrate. The electrical connection between the interposer and the coreless substrate includes wire bonding and conductive microvias, and the coreless substrate can provide a fan-out route from the interposer.

Description

technical field [0001] The invention relates to a semiconductor component, especially a semiconductor component with a flip-chip semiconductor element on an interposer, wherein the interposer is fixed on a coreless substrate. The intermediary layer has a through hole, and the connection between the intermediary layer and the coreless substrate is flexibly connected through conductive micro-holes and wire bonding. Background technique [0002] High-performance semiconductor chips usually use a dielectric layer with a low-k value as an interlayer material. When the dielectric material with low-k value is porous, fragile, and very sensitive to interface stress, traditional flip-chip packaging with laminated substrates will face problems due to the low-k value chip and the thermal expansion coefficient between the laminated substrates. Matching, which leads to various reliability problems and pass rate problems. In order to solve the above problems, attempts have been made to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/498
CPCH01L24/73H01L2224/04105H01L2224/16145H01L2224/16225H01L2224/48227H01L2224/73253H01L2224/73259H01L2224/73277H01L2224/92144H01L2924/15311H01L2924/15192H01L2924/19107H01L2224/45144H01L2224/0401H01L2924/181H01L2224/19H01L2924/3511H01L2924/00H01L2924/00012
Inventor 林文强王家忠
Owner BRIDGE SEMICON
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