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Method for suppressing gate polysilicon depletion in pmos device process

A polysilicon depletion, polysilicon technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as metal ion pollution, gate structure morphology has a great influence, unfavorable device performance stability, etc., reaching the threshold Effects of Voltage Stabilization and Suppression of Gate Polysilicon Depletion Phenomenon

Active Publication Date: 2017-03-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the above method can suppress the depletion of gate polysilicon, the newly introduced titanium is easily oxidized and expanded in the subsequent gate polysilicon re-oxidation (Re-oxidation) process, resulting in spherical protrusions (pilling), which It will greatly affect the morphology of the gate structure, which is not conducive to the stability of the device performance
At the same time, the introduction of titanium also poses a risk of metal ion contamination to products on the process line

Method used

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  • Method for suppressing gate polysilicon depletion in pmos device process
  • Method for suppressing gate polysilicon depletion in pmos device process
  • Method for suppressing gate polysilicon depletion in pmos device process

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Embodiment Construction

[0018] Such as image 3 As shown, it is a flow chart of the method of the embodiment of the present invention; the method for suppressing the depletion of gate polysilicon in the PMOS device process in the embodiment of the present invention includes the following steps:

[0019] Step one, such as Figure 4A As shown, a gate dielectric layer 2 and a gate polysilicon 3 are sequentially formed on a silicon substrate 1, wherein the gate dielectric layer 1 can be an oxide layer. After the gate polysilicon 3 is formed, boron ions are implanted into the gate polysilicon 3 in the PMOS device formation area, the energy of implanting boron ions is 3KeV-8Kev, and the implantation dose is 1E15cm -2 ~1E16cm -2 , making the gate polysilicon 3 in the region where the PMOS device is formed have a P-type doped structure.

[0020] Step two, such as Figure 4A As shown, after boron ion implantation, nitrogen ion implantation is performed on the surface of the gate polysilicon 3 in the PMOS ...

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Abstract

The invention discloses a method for inhibiting depletion of a grid polysilicon in a PMOS (p-channel metal oxide semiconductor) device technology. The method comprises the following steps: implanting boron ions into the grid polysilicon; implanting nitrogen ions on the surface of the grid polysilicon; forming a wolfram silicon layer on the surface of the grid polysilicon. Through nitrogen ion implantation after boron ion implantation into the grid polysilicon of a PMOS device, a dense nitride film can be formed on the surface of the grid polysilicon, and the nitride film can prevent boron from diffusing to the surface of the grid polysilicon and can reduce a risk that in the subsequent thermal process, boron is promoted to penetrate into the wolfram silicon layer, so that the depletion of the grid polysilicon caused by boron penetration into a WSI (wolfram silicon layer) in the PMOS device technology can be effectively inhibited, and the threshold voltage of the PMOS device is stable.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for suppressing gate polysilicon depletion (Poly Depletion Effects) in a PMOS process. Background technique [0002] In the existing process, in order to facilitate the integration of NMOS devices, the gate polysilicon of PMOS devices adopts the same doping conditions as the gate polysilicon of NMOS devices, that is, both are N-type doped and require heavy doping, and the gate polysilicon of PMOS devices After N-type doping of extremely polysilicon, a P-type buried channel (buried channel) must be formed in the channel region to solve the problem of high threshold voltage (Vt) caused by N-type gate polysilicon, and the introduction of P-type buried channel will cause A large leakage current problem occurs. In order to solve the problems of higher Vt and larger leakage current caused by the buried channel of the existing PMOS device, P-ty...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28
CPCH01L21/28044
Inventor 陈瑜罗啸李喆
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP