Method for suppressing gate polysilicon depletion in pmos device process
A polysilicon depletion, polysilicon technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as metal ion pollution, gate structure morphology has a great influence, unfavorable device performance stability, etc., reaching the threshold Effects of Voltage Stabilization and Suppression of Gate Polysilicon Depletion Phenomenon
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[0018] Such as image 3 As shown, it is a flow chart of the method of the embodiment of the present invention; the method for suppressing the depletion of gate polysilicon in the PMOS device process in the embodiment of the present invention includes the following steps:
[0019] Step one, such as Figure 4A As shown, a gate dielectric layer 2 and a gate polysilicon 3 are sequentially formed on a silicon substrate 1, wherein the gate dielectric layer 1 can be an oxide layer. After the gate polysilicon 3 is formed, boron ions are implanted into the gate polysilicon 3 in the PMOS device formation area, the energy of implanting boron ions is 3KeV-8Kev, and the implantation dose is 1E15cm -2 ~1E16cm -2 , making the gate polysilicon 3 in the region where the PMOS device is formed have a P-type doped structure.
[0020] Step two, such as Figure 4A As shown, after boron ion implantation, nitrogen ion implantation is performed on the surface of the gate polysilicon 3 in the PMOS ...
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