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Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array)

A parallel processing and multi-serial port technology, which is applied in the direction of electrical digital data processing and instruments, can solve the problems of increased hardware cost, limited hardware serial interface resources, and long CPU waiting time, so as to reduce design complexity and difficulty and improve Data transmission bandwidth and effect of reducing CPU load

Inactive Publication Date: 2014-04-09
STATE NUCLEAR POWER AUTOMATION SYST ENGCO
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such as 8250, 16550AFN and other chips are common UART devices, but the hardware serial interface resources of these devices are limited, and the internal structure design is quite complicated, with many chip pins, and some contain many auxiliary modules (such as FIFO). Only the basic functions of UART are often used in use, and such chips are used in design, resulting in waste of resources; 2) The number of scalable serial ports provided by processors or dedicated multi-serial port chips is limited, and more UART serial port expansion cannot be realized; 3. ) The peripheral interface circuit is complex, and the board design is more difficult; 4) The use of UART chips will also increase the hardware cost and increase the area of ​​​​the circuit board, which cannot be used in large-scale multi-channel data acquisition occasions; 5) The processor adopts serial mode Scan each channel in turn, but the serial port communication rate is too low, resulting in too long CPU waiting time, it is difficult to meet the actual needs of high real-time requirements and parallel processing

Method used

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  • Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array)
  • Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array)
  • Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array)

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Embodiment Construction

[0013] In order to realize the support of parallel multi-channel serial peripherals, increase the UART bus serial communication bandwidth, reduce the CPU load, improve system integration, and reduce hardware costs, such as figure 2 As shown, the present invention is based on the multi-serial port parallel processing framework of SoCFPGA, comprises transceiver, the SoC FPGA chip that integrated Field Programmable Logic Array FPGA and processor CPU, CPU is connected with FPGA by internal bus, it is characterized in that: described SoC The FPGA in the FPGA chip internally designs a plurality of UART cores and a plurality of coprocessor MCUs corresponding to each UART core through a hardware description language; the FPGA is embedded with a plurality of embedded memories corresponding to each coprocessor MCU, Each embedded memory is configured as a dual-port mode capable of reading and writing operations; the multiple UART cores are connected to multiple corresponding transceivers...

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Abstract

The invention belongs to the field of a distributed industrial control technology, and relates to a multi-serial port parallel processing framework based on a SoC (System on a Chip) FPGA (Field Programmable Gata Array). The framework comprises transceivers, and a SoC FPGA chip which is integrated with an FPGA and a processor CPU. The framework is characterized in that a plurality of UART (Universal Asynchronous Receiver / Transmitt) cores and a plurality of coprocessor MCUs (Microprogrammed Control Unit) corresponding to the UART cores are designed in the FPGA in the SoCFPGA chips according to an HDL (Hardware Description Language); a plurality of embedded memories corresponding to the coprocessoer MCUs are embedded into the FPGA, and each embedded memory is configured to be in a dual-port mode capable of reading and writing; and the plurality of UART cores and a plurality of corresponding transceivers are connected through RS232 / RS422 / RS485 interfaces. The device is high in system integration degree and low in hardware design cost, is capable of effectively reducing CPU load, promoting the transmission bandwidth of serial bus data, and flexibly expanding a plurality of serial channels.

Description

technical field [0001] The invention belongs to the technical field of distributed industrial control, and in particular relates to a SoC FPGA-based multi-serial port parallel processing architecture. Background technique [0002] UART (Universal Asynchronous Receiver Transmitter) is a serial transmission interface widely used in short-distance, low-speed communication. It is easy to operate, reliable in operation, strong in anti-interference, low in cost, and long in transmission distance (comprising 485 networks can transmit 1,200 meters above). In data communications, computer networks, and distributed industrial control systems, processors often use serial communications to exchange data and information with peripheral modules. [0003] In modern industrial control systems, multi-serial communication is used more and more widely. Especially in the field of data acquisition, the demand for the number of serial ports in engineering applications increases, and the process...

Claims

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Application Information

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IPC IPC(8): G06F13/20
Inventor 刘玉升王楠
Owner STATE NUCLEAR POWER AUTOMATION SYST ENGCO
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