Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array)
A parallel processing and multi-serial port technology, which is applied in the direction of electrical digital data processing and instruments, can solve the problems of increased hardware cost, limited hardware serial interface resources, and long CPU waiting time, so as to reduce design complexity and difficulty and improve Data transmission bandwidth and effect of reducing CPU load
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[0013] In order to support parallel multi-channel serial peripherals, increase the UART bus serial communication bandwidth, reduce the load of the CPU, improve system integration, and reduce hardware costs, such as figure 2 As shown, the multi-serial parallel processing architecture of the present invention based on SoCFPGA includes a transceiver, a SoC FPGA chip integrated with a field programmable logic array FPGA and a processor CPU. The CPU is connected to the FPGA through an internal bus, and is characterized in that: the SoC The FPGA in the FPGA chip uses hardware description language to design multiple UART cores and multiple coprocessor MCUs corresponding to each UART core; the FPGA embeds multiple embedded memories corresponding to each coprocessor MCU, Each embedded memory is configured in a dual-port mode capable of reading and writing operations; the multiple UART cores are connected with multiple corresponding transceivers through RS232 / RS422 / RS485 interfaces.
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