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Sampling hold switch circuit

一种开关电路、采样保持的技术，应用在采样保持开关电路领域，能够解决采样场效应管线性度下降、无法满足高速度、制约采样保持开关电路动态范围等问题，达到提高线性度、提高采样性能的效果

Inactive Publication Date: 2014-04-30
IPGOAL MICROELECTRONICS (SICHUAN) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the increase of sampling frequency, the linearity of sampling FETs with traditional structures continues to decline, which restricts the dynamic range of the sample-and-hold switch circuit and cannot meet the requirements of high-speed, high-performance analog-to-digital converters for the dynamic performance of sampling signals.

Method used

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Embodiment Construction

[0017] Embodiments of the present invention will now be described with reference to the drawings, in which like reference numerals represent like elements. As mentioned above, the present invention provides a sample-and-hold switch circuit, which reduces the nonlinearity of the sampling FET due to the variation of the gate-source voltage with the input signal, and simultaneously eliminates the body effect of the sampling FET , which further improves the linearity of the sampling FET and improves the dynamic range of the sampling and holding switching circuit.

[0018] Please refer to figure 1 , figure 1 It is a circuit structure diagram of the sample-and-hold switch circuit of the present invention. The sample-and-hold switch circuit of the present invention includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling field effect transistor MS, a holding capacitor CS and a substrate selection sub-circuit. The clock generation sub-circuit has a first o...

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Abstract

The invention discloses a sampling hold switch circuit. The sampling hold switch circuit comprises a clock generating sub circuit, a grid voltage bootstrap unit, a sampling field-effect tube and a holding capacitor, and further comprises a substrate selection sub circuit which is respectively connected with a signal input end, a signal output end and a substrate of the sampling field-effect tube. The substrate selection sub circuit is used for selecting the signal input end or the signal output end to be connected with the substrate of the sampling field-effect tube according to the voltage values of an input analog signal and an output analog signal to eliminate the bulk effect of the sampling field-effect tube. According to the sampling hold switch circuit, the nonlinearity, produced when the grid source voltage changes along with the input signal, of the sampling field-effect tube is reduced, the bulk effect of the sampling field-effect tube is eliminated, the linearity of the sampling field-effect tube is further improved, and the dynamic range of the sampling hold switch circuit is enlarged.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a sample-and-hold switch circuit for sampling analog signals. Background technique [0002] In today's high-speed and high-precision ADC (Analog-to-Digital Converter, analog-to-digital converter) circuits, the sample-and-hold switch circuit is the bottleneck of the entire converter design, and the sampling FET is an indispensable part of the sampling circuit , The speed and precision of the sampling FET determine the overall performance of the sampling and holding switching circuit to a large extent. Under deep submicron process conditions, the sampling FET connected to the input signal is connected with a grid voltage bootstrap structure to reduce the on-resistance of the sampling FET, reduce the nonlinearity of the sampling FET and expand the input signal range . However, as the sampling frequency increases, the linearity of the traditional structure of the sampling FET con...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/54
CPCH03K17/145H03K17/161H03K2217/0054G11C27/024H03K17/6871G11C11/00
Inventor 杨保顶邹铮贤
Owner IPGOAL MICROELECTRONICS (SICHUAN) CO LTD
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