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Distance compression operational circuit of imaging processing of synthetic aperture radar

A synthetic aperture radar and distance compression technology, applied in the field of telemetry and remote sensing, can solve the problems of difficulty in ensuring reliability, high requirements for coordinated control of two data processing circuits, complex structure, etc., and achieves high reliability, simple connection and control methods. Effect

Inactive Publication Date: 2014-05-14
XIDIAN UNIV
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Problems solved by technology

The circuit structure of this set is relatively complex, and the coordination control requirements of the two-way data processing circuits are also relatively high, and the reliability is difficult to guarantee

Method used

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  • Distance compression operational circuit of imaging processing of synthetic aperture radar

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Embodiment 1

[0016] The circuit composition, connection mode and function are the same as the above-mentioned specific implementation mode. Here, the selection and working mode of key circuit components are further described in detail:

[0017] Programmable logic array chip FPGA adopts TMS320C6455 chip of Texas Instruments Company, and configures its operating frequency as 1GHz, and the corresponding processing speed is 8000MIPS; configures its data reading method for first-in-first-out memory as DMA method.

[0018] The external memory adopts DDR2 standard synchronous dynamic random access memory SDRAM, its main frequency is 500Mhz, the corresponding core operating frequency is 125Mhz, the capacity is 8Mbytes, and it is designed as a 256K*32bit structure.

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Abstract

The invention relates to a distance compression operational circuit of imaging processing of a synthetic aperture radar. The distance compression operational circuit consists of a programmable logic array chip FPGA, an external memory, an output interface, a FIFO (first in first out) memory and a clock drive circuit, wherein the programmable logic array chip FPGA contains an external memory interface A having a 64 bit architrave and adaptive to an SRAM (static random access memory), a DDR2 external memory interface, a phase-locked loop controller and a host interface. The distance compression operational circuit is characterized in that the external memory interface A having the 64 bit architrave of the programmable logic array chip FPGA is separated into two parts in using functions, a half includes a 32 bit architrave for receiving data from the FIFO memory, and the other half includes a 32 bit architrave for outputting an operational result to an output interface. A circuit structure, a connection mode and a control method are simple, the reliability is high, and thus a requirement for real-time performance of data processing is satisfied.

Description

technical field [0001] The invention relates to remote measurement and remote sensing technology, in particular to a remote measurement and remote sensing information processing technology for Synthetic Aperture Radar (SAR) imaging. Background technique [0002] Synthetic Aperture Radar (SAR) is a high-resolution microwave imaging radar. It is usually installed on an aircraft or satellite to image the ground. The resulting image corresponds to a large object size and a large amount of image data. With the development of modern synthetic aperture radar in the direction of high resolution, high swath, multi-band, multi-polarization, multi-mode, etc., the amount of image data processing continues to increase. In the process of SAR imaging processing, range compression processing is an indispensable one. step, due to its large amount of computation and high computation speed requirements, it is easy to form a bottleneck in digital signal processing, so the distance compression p...

Claims

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Application Information

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IPC IPC(8): G01S7/02G01S13/90
CPCG01S7/02G01S13/90G01S13/9004
Inventor 廖轶邢孟道张磊
Owner XIDIAN UNIV
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