A method for semiconductor packaging by utilizing connection pieces to realize connection

Abstract

The invention discloses a semiconductor package body in which inner connection is realized through connection pieces. The semiconductor package body comprises a plurality of chips, wherein each chip is provided with a plurality of top contact areas and bottom contact areas; a plurality of substrates which are used for placing the chips, the bottom contact areas of the chips being in electrical connection with the substrates, and the substrates being provided with a plurality of substrate outer pins; connection pieces, wherein the connection pieces are connected with the plurality of chips and are used for connecting with the plurality of top contact areas arranged corresponding to the plurality of chips, thereby fixing the plurality of chips, the end portions of the connection pieces being as the pins of the chips so as to connect with external circuits; and a plastic package body which is used for packaging the chips, the substrates and the connection pieces. During the production process of the semiconductor package body, the plurality of chips are fixedly connected by utilizing one or the plurality of connection pieces; then packaging is carried out; and at last, the connection pieces are separated through cutting or package body top grinding. Since the fixation connection effect of the connection pieces, the influence, due to malposition of the chips in the production process, on the circuit performance is prevented.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a manufacturing method, in particular to a semiconductor packaging and a manufacturing method thereof which are connected by connecting sheets. Background technique [0002] In order to meet the needs of miniaturization of electronic products, multi-chip semiconductor packaging has become a trend, and the semiconductor packaging of multi-chip modules carries multiple chips in a single package. [0003] For example, in the Chinese patent authorization announcement number CN201063342Y, a multi-chip packaging structure is disclosed, including: a first lead frame, including a first chip seat, a first inner pin and a second outer pin; a second lead frame, including a first Two chip seats and second inner pins; the second lead frame is located above or below the first lead frame, and the first lead frame is electrically connected to the second lead frame through the connector; the first chip is...

AI Technical Summary

Problems solved by technology

[0005] The above-mentioned prior art for chip packaging is to use wires for the connection between the chip and the lead frame, but in the packaging process of multiple chips connected by wires, the bonding and soldering reflow process usually make the chips prone to error. Movement, and due to the movement of the chip, a short circuit between the wires is caused at the same time, which affects the performance of the circuit. In addition, in the prior art, in order to increase the pins, cutting is performed at the bottom of the package, which has poor flexibility and increases the complexity of the process. , is not conducive to reducing production costs

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