Semiconductor device and manufacture method thereof

Abstract

The invention discloses a manufacture method of a semiconductor device. The method comprises the following steps: forming a plurality of fins extending along a first direction on a substrate; forming a cover layer on the top of each fin; forming a false grid stack structure extending along a second direction on each fin and each cover layer; forming grid side walls at the two sides, along the first direction, of the false grid stack structure, the grid side walls being on the cover layers; removing the false grid stack structures and forming grid grooves; and forming a grid stack structure in each grid groove. According to the semiconductor device and the manufacture method thereof, the relatively-thick cover layers are added additionally after the fins are formed so as to prevent the fins from being damaged in the follow-up etching process, thereby improving the performance and reliability of the device effectively.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional multi-gate FinFET capable of avoiding silicon fin etching damage and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness ...

AI Technical Summary

Problems solved by technology

[0005] It is worth noting that in the above-mentioned 3D multi-gate FinFET, since there is no thicker SiO 2 or other insulating layer protection, in the subsequent etching process, including dummy gate strip etching, sidewall etching and other processes, due to the need for a large number of over-etching steps to eliminate the parasitic dummy gates or sidewalls on both sides of the silicon Fin, These processes will cause etching damage on the top of silicon Fin, and the ultra-thin dummy gate insulating layer cannot provide etching selective protection for excessive over-etching processes

These damages will affect the performance of the device channel region and reduce the overall performance and reliability of the device

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