Synchronization pulse jitter suppression method and system based on fpga

Abstract

The invention discloses a synchronous pulse jitter suppression method and system based on an FPGA. Reaching time of external pulses is recorded and buffered onto a BlockRAM of an FPGA sheet, then, next synchronous pulse reaching time is predicated, and a local synchronous pulse is triggered to be generated according to the next synchronous pulse reaching time, so that jitter removal is realized, shortening of capturing time and high jitter restriction can be realized at the same time, and the jitter performance and the stability of regenerated synchronous pulses are improved. The method and system are suitable for occasions which are used for processing low and medium frequence synchronous signals and are high in instantaneity requirement.

Description

technical field [0001] The invention relates to an FPGA-based synchronization pulse jitter suppression method and system, belonging to the technical fields of data acquisition, communication and testing. Background technique [0002] At present, the time-division multiplexing digital communication network is extremely dependent on the synchronization signal. If the locally recovered synchronization signal has a large jitter, in some cases, it may cause the deterioration of the equipment performance and lead to data sampling errors, resulting in communication errors. In a cascaded communication system, synchronous jitter will cause a position modulation of the regenerated signal, which not only deteriorates the signal-to-noise ratio at the moment of regeneration decision, but also reflects in the regenerated signal and transmits it to the next repeater. The accumulation along the relay chain limits the communication distance, and the existence of timing jitter makes the recei...

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Problems solved by technology

[0008] Although the above synchronization jitter suppression method can effectively eliminate part of the delay jitter in the external synchronization signal, it has its own shortcomings. The sender of method 1) must use a high stable time base while ensuring low jitter in the transmission process, which is difficult Larger; method 2) requires complex circuits such as VCO and DAC, the cost is high, and based on the Kalman filter algorithm, it includes matrix inversion operations and matrix multiplication operations and other iterative processes. The operations are more complicated and difficult to implement on the FPGA platform; method 3 ) In the scheme of using the phase-locked loop, either a simple single-loop scheme is used, resulting in the inability to achieve the short capture time and narrow loop bandwidth at the same time, or the use of a complex double-loop plus VCXO scheme makes the entire cost And the complexity increases and the reliability decreases. Moreover, all phase-locked loops without exception introduce negative feedback loops, resulting in longer loop locking time and affecting real-time performance.

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