Sampling clock generation circuit for multichannel time interleaving analog-digital converter

Abstract

The invention relates to a sampling clock generation circuit for a multichannel time interleaving analog-digital converter. The sampling clock generation circuit for the multichannel time interleaving analog-digital converter is composed of a multiphase clock generation module, a duty ratio recovering circuit and a channel selection module, wherein the multiphase clock generation module generates a multiphase clock signal required by the multichannel analog-digital converter and compensates for the a phase error of the multiphase clock signal at the same time, so that the accuracy of sampling clocks between channels of the analog-digital converter is guaranteed; the duty ratio recovering circuit conducts edge adjustment on a multiphase clock generated by the multiphase clock generation module, namely duty ratio recovery is conducted, and the output multiphase clock signal serves as a sampling clock signal of a sampling hold circuit; the channel selection module receives a control code written in through an external serial port, judges the number of required internal channels, controls the opening and closing of the internal channels and selects a multiphase clock inside a multiphase pulse module according to the control code, so that sampling clock generation is achieved under the condition that different channels are selected.

Description

technical field [0001] The invention relates to a sampling clock generating circuit for a multi-channel time-interleaved analog-to-digital converter, which belongs to the field of integrated circuit mixed signal design and is mainly used in a multi-channel time-interleaved converter to reduce the error of the sampling clock and improve the performance of the converter . Background technique [0002] In 1980, Black and Hodges proposed multi-channel time-interleaved ADC technology for the first time. This technology uses multiple low-sampling-rate sub-ADCs to work in parallel, and samples the same input signal through sampling clock interleaving to increase the sampling rate. This technology realizes the same sampling The requirements of each sub-ADC are reduced under the condition of low rate, which makes it more and more used in high-speed and high-precision converters. [0003] Although the multi-channel time-interleaved analog-to-digital converter can increase the samplin...

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Problems solved by technology

The delay-locked loop can set the number of delay units inside the controllable delay line 304 to obtain clock signals of equal phases with different phase difference accuracy, but the delay-locked loop requires the phase difference between the input clock signal and the feedback clock signal in order to achieve locking. is zero, that is to say, the feedback clock signal is obtained by delaying the input clock signal by an integer number of clock cycles, which increases the difficulty of the design of the entire loop. In order to ensure high phase alignment accuracy, the number of delay units will be large. If it is realized by digital method, it is difficult to ensure its high-frequency operation. If it is realized by analog method, it is necessary to ensure that the delay unit has good noise suppression ability. Any noise coupled from power supply and substrate will affect its operation when the converter is working. The accuracy of the phase alignment, and the mismatch of the clock distribution path of each multi-channel sampling clock in the clock distribution network 305 will further increase the error of the multi-channel sampling clock

[0009] In a multi-channel time-interleaved high-speed high-precision analog-to-digital converter, the gain error, offset error and sampling clock error between channels will affect the static and dynamic performance of the converter, reduce the conversion accuracy, and need to be calibrated for errors. The sampling clock error has become the bottleneck in the design of ultra-high-speed data converters. It is difficult to obtain good results by statistically extracting the sampling clock error between channels and compensating the output data of the converter. Therefore, how to better obtain multi-channel sampling clock It has become a trend in current circuit design

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