Semiconductor device of novel package structure

Abstract

The invention discloses a semiconductor device of a novel package structure. The semiconductor device comprises an image sensing chip and a transparent cover plate. A metal conductive pattern layer which is electrically connected with a pin bonding pad is arranged in a blind hole and on the surface, opposite to the image sensing chip, of a passivating layer. A supporting cofferdam is composed of a first supporting cofferdam layer and a second supporting cofferdam layer which are overlapped up and down. The first supporting cofferdam layer is in contact with the transparent cover plate. The second supporting cofferdam layer is in contact with the image sensing chip. A plurality of V-shaped continuous notches are formed in the inner side face of the second supporting cofferdam layer. Arc notches are formed in the four corners of the second supporting cofferdam layer respectively. The metal conductive pattern layer is formed by sequentially overlapping a titanium layer, a copper layer, a nickel layer and a palladium layer. The titanium layer and the passivating layer are in contact. The semiconductor device relieves stress, is exposed in the environment, and can not be easily oxidized and corroded, stress deformation of metal on the two sides of the blind hole under the cold and hot environments is effectively buffered, the response time of the semiconductor device is shortened, and the requirement that the metal layer continuously covers the inner wall of the deep hole with a high aspect ratio is met.

Description

technical field [0001] The invention relates to a semiconductor device with a novel packaging structure, belonging to the technical field of semiconductor packaging. Background technique [0002] Semiconductor devices refer to silicon wafers used in the production of silicon semiconductor integrated circuits. Because of their circular shape, they are called wafers; they can be processed into various circuit element structures on silicon wafers, and become ICs with specific electrical functions. product. The existing wafer-level chip packaging structure mainly has the following technical problems: [0003] (1) The existing metal yields filled in the blind holes on the wafer have certain limitations, high stress, low reliability level, and are easily oxidized and corroded in the exposed environment, resulting in product failure and stable chemical properties Poor, and with the development of wafer-level packaging through-hole silicon interconnection technology in the directi...

AI Technical Summary

Problems solved by technology

Due to the limitation of overflowing glue, the width of the cofferdam is relatively large, which directly affects the reliability of CIS products and is prone to delamination.

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