The invention discloses a
wafer-level
chip packaging structure. The
wafer-level
chip packaging structure comprises an
image sensing chip and a transparent cover plate, wherein
metal conductive pattern
layers electrically connected with pin bonding pads are arranged on the surface, with the back towards the
image sensing chip, of a
passivation layer and blind holes respectively. Each supporting
cofferdam is composed of a first supporting
cofferdam layer and a second supporting
cofferdam layer which are placed in a vertically stacked mode, a plurality of continuously arranged V-shaped notched are formed in the inner side face of each second supporting cofferdam layer, arc-shaped notches are formed in the four corners of each second supporting cofferdam layer respectively, a plurality of holes are evenly formed in the surface, in contact with the
image sensing chip, of each supporting cofferdam, each
metal conductive pattern layer is formed by placing a
titanium layer, a
copper layer, a
nickel layer and a
palladium layer in a stacked mode in sequence, and the
titanium layers are in contact with the
passivation layer. According to the
wafer-level chip packaging structure, stress is relieved, the structure is not prone to oxidation
corrosion, the
response time of a device is shortened, the reliability of a product is improved, and the requirement for continuously covering the inner wall of a
deep hole with a high aspect ration with a
metal layer can be met.