Wafer-level chip packaging structure

A wafer-level chip and packaging structure technology, applied in radiation control devices and other directions, can solve the problems affecting the reliability and delamination of CIS products, and achieve the effects of high reliability, good chemical properties, and stress relief

Active Publication Date: 2014-07-30
苏州科阳半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the limitation of overflowing glue, the width of the cofferdam is relatively large, which directly affects the reliability of CIS products and is prone to delamination.

Method used

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  • Wafer-level chip packaging structure
  • Wafer-level chip packaging structure
  • Wafer-level chip packaging structure

Examples

Experimental program
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Effect test

Embodiment 1

[0018] Embodiment 1: A wafer-level chip packaging structure, including an image sensor chip 1 and a transparent cover plate 2, the upper surface of the image sensor chip 1 has a photosensitive area 3, and the edge of the transparent cover plate 2 and the image sensor There is a support bank 4 between the upper surface edge of the chip 1 so as to form a cavity 13 between the transparent cover plate 2 and the image sensor chip 1, and the support bank 4 and the image sensor chip 1 are bonded by a glue layer 5 In combination, there are several blind holes 6 distributed around the edge area around the lower surface of the image sensor chip 1, the lower surface of the image sensor chip 1 and the side surfaces of the blind holes 6 have a passivation layer 7, and the bottom of the blind hole 6 has an image sensor The pin pad 8 of the sensor chip 1, the surface of the passivation layer 7 opposite to the image sensor chip 1 and the blind hole 6 have a metal conductive pattern layer 9 ele...

Embodiment 2

[0020] Embodiment 2: A wafer-level chip packaging structure, including an image sensor chip 1 and a transparent cover plate 2, the upper surface of the image sensor chip 1 has a photosensitive area 3, and the edge of the transparent cover plate 2 and the image sensor There is a support bank 4 between the upper surface edge of the chip 1 so as to form a cavity 13 between the transparent cover plate 2 and the image sensor chip 1, and the support bank 4 and the image sensor chip 1 are bonded by a glue layer 5 In combination, there are several blind holes 6 distributed around the edge area around the lower surface of the image sensor chip 1, the lower surface of the image sensor chip 1 and the side surfaces of the blind holes 6 have a passivation layer 7, and the bottom of the blind hole 6 has an image sensor The pin pad 8 of the sensor chip 1, the surface of the passivation layer 7 opposite to the image sensor chip 1 and the blind hole 6 have a metal conductive pattern layer 9 ele...

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PUM

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Abstract

The invention discloses a wafer-level chip packaging structure. The wafer-level chip packaging structure comprises an image sensing chip and a transparent cover plate, wherein metal conductive pattern layers electrically connected with pin bonding pads are arranged on the surface, with the back towards the image sensing chip, of a passivation layer and blind holes respectively. Each supporting cofferdam is composed of a first supporting cofferdam layer and a second supporting cofferdam layer which are placed in a vertically stacked mode, a plurality of continuously arranged V-shaped notched are formed in the inner side face of each second supporting cofferdam layer, arc-shaped notches are formed in the four corners of each second supporting cofferdam layer respectively, a plurality of holes are evenly formed in the surface, in contact with the image sensing chip, of each supporting cofferdam, each metal conductive pattern layer is formed by placing a titanium layer, a copper layer, a nickel layer and a palladium layer in a stacked mode in sequence, and the titanium layers are in contact with the passivation layer. According to the wafer-level chip packaging structure, stress is relieved, the structure is not prone to oxidation corrosion, the response time of a device is shortened, the reliability of a product is improved, and the requirement for continuously covering the inner wall of a deep hole with a high aspect ration with a metal layer can be met.

Description

technical field [0001] The invention relates to a wafer-level chip packaging structure, which belongs to the technical field of semiconductor packaging. Background technique [0002] Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because of its circular shape, it is called a wafer; it can be processed into various circuit element structures on the silicon wafer, and become an IC with specific electrical functions. product. The existing wafer-level chip packaging structure mainly has the following technical problems: [0003] (1) The existing metal yields filled in the blind holes on the wafer have certain limitations, high stress, low reliability level, and are easily oxidized and corroded in the exposed environment, resulting in product failure and stable chemical properties Poor, and with the development of wafer-level packaging through-hole silicon interconnection technology in the direction of high aspect ratio, i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/146
Inventor 赖芳奇吕军张志良陈胜
Owner 苏州科阳半导体有限公司
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