SiGe body region longitudinal 1T-DRAM device and manufacturing method thereof

Abstract

The invention provides a longitudinal nano-pillar 1T-DRAM device and array based on SiGe energy-band engineering. A longitudinal nano-pillar transistor is adopted, laminated layers formed through epitaxy serve as a channel region and a drain region respectively, large space is provided for design of the channel region and the drain region, and many implementation schemes are provided for promoting the 1T-DRAM performance. Meanwhile, the structure of the longitudinal transistor is beneficial to integration of the SiGe channel region; epitaxy SiGe is adopted as the channel region, a potential well of a hole is formed in the channel region by means of the difference between the valence band of the SiGe and the valence band of Si, and therefore the current difference between the 1-reading state and the 0-reading state of a 1T-DRAM.

Description

technical field [0001] The invention relates to the field of semiconductor devices and manufacturing methods thereof, in particular to a vertical high-integration transistor structure based on SiGe energy band engineering and a manufacturing method thereof. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, the size of the traditional 1T / 1C embedded DRAM unit is shrinking, and the area of ​​its capacitor is becoming more and more difficult with scaling down (scalingdown), and the manufacturing process is becoming more and more complicated. , The compatibility with the logic device process is getting worse and worse. Therefore, capacitorless DRAM (Capacitorless DRAM) with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM of VLSI. Among them, 1T-DRAM (One Transistor Dynamic Random Access Memory) utilizing floating body effect is th...

AI Technical Summary

Problems solved by technology

[0005] At present, the structure of IT-DRAM is generally based on SOI planar structure, and the main problem of 1T-DRAM with SOI planar structure is that the potential of the body region is limited by the hole barrier between the body region and the source and drain.

In addition, the SOI substrate is not compatible with the currently widely used bulk silicon process, and there is a problem that it is not easy to dissipate heat

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