Manufacturing method of semiconductor package

Abstract

A method for manufacturing a semiconductor package, which includes: placing a semiconductor chip on the top surface of a metal substrate, the top surface of the metal substrate has a plurality of protruding conductive pins; electrically connecting the semiconductor chip and the conductive lead foot; forming encapsulant on the top surface of the metal substrate; forming a barrier layer on the outer edge of the bottom surface of the metal substrate; etching the bottom surface of the metal substrate to remove the metal substrate not covered by the barrier layer part of the thickness, and make the second surface of the metal substrate define a protrusion on the outer edge; form a patterned resistance layer corresponding to each of the conductive pins on the bottom surface of the metal substrate; etch the bottom surface of the metal substrate, removing the metal substrate not covered by the patterned resist layer; removing the patterned resist layer; and performing a cutting step to remove the protrusion. The invention can effectively improve the efficiency of the package.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor package, in particular to a method for manufacturing a quadrangular plane leadless semiconductor package. Background technique [0002] Quad Flat No Lead (QFN for short) semiconductor package is a package unit in which the bottom surface of the pin is exposed on the bottom surface of the packaging layer. The leadless semiconductor package is connected to the printed circuit board to form a circuit module with specific functions. [0003] With the development of thinner and smaller electronic components, the thickness of semiconductor packages has become one of the key points in the development of the packaging field. figure 1 The one shown is a cross-sectional view of a conventional pre-etched semiconductor package, which is manufactured by first providing a pre-etched lead frame (leadframe) 10, and the top surface of the lead frame 10 has a plurality of protruding conductive pins 10...

AI Technical Summary

Problems solved by technology

[0004] However, because the pre-etching is comprehensive etching, that is, the bottom surface of the lead frame 10 is fully etched, so there is no reference point for reference or measurement of the etched depth and the lead frame 10 after the pre-etching is completed. The remaining thickness R of the remaining thickness R, that is, the etched depth and the remaining thickness of the lead frame 10 cannot be known, so the heights of the conductive pins 101a and the crystal pads 101b cannot be known, which will affect the standing height (stand) of the pins of the final semiconductor package. off) and the coplanarity between the conductive pins 101a, and lead to yield problems of semiconductor packages, resulting in increased manufacturing costs

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