Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a SiGe layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent Fins are selectively thinned so as to prevent an undesired bridging of SiGe material between immediately adjacent ones of the Fins. A method of manufacturing the same comprises: providing a substrate having a plurality of tri-gate transistors, at least two fins of the tri-gate transistors being closely adjacent to each other, where respective top and sidewall surfaces of the fins are coated with a SiGe layer; performing a tilted ion implantation on the SiGe coated fins so as to partially convert the SiGe material into a predetermined etch resistant material (e.g., and oxide of the SiGe); and etching away the non-converted sidewall parts of the SiGe coating layers so as to provide greater spacing between the immediately adjacent sidewalls of the SiGe coated fins.

Description

technical field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to a semiconductor device capable of increasing a space between SiGe layers of adjacent fins (Fin) of a tri-gate transistor and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology, the critical dimensions of semiconductor devices are continuously reduced. Under this trend, the proposed figure 1 Tri-gate transistors shown, also known as 3D transistors. The planar gates in traditional 2D transistors are replaced by ultra-thin 3D silicon fins that rise vertically from the silicon substrate. [0003] In 3D transistors, the silicon fins are all vertical, so that the transistors can be placed closer together, greatly increasing transistor density. Furthermore, in 3D transistors, current control is achieved by installing a gate in each of the three sides of the fin (i.e., two sides ...

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Problems solved by technology

[0005] However, with the miniaturization of CDs, in the manufacturing process of 3D transistors, such as figure 2 As shown, the SiGe layer of a fin of a MOS transistor can easily bridge the SiGe layer of its adjacent fin, thereby degrading the performance of the 3D transistor

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