Formation method of dual damascene structure

A patterned, bottom anti-reflection layer technology, which is applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems that the inner wall of the double damascene structure is not flat enough, affects the quality of the metal layer, and affects the performance of the metal interconnection structure, etc. , to achieve the effects of improving electrical connection performance, avoiding damage, and uniform etching rate

Inactive Publication Date: 2014-10-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Claims
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AI Technical Summary

Problems solved by technology

[0012] The inner wall of the double damascene structure formed by the existing technology is not smooth enough, which will affect the quality of the metal layer filled in later, and affect the performance of the metal interconnection structure formed subsequently

Method used

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  • Formation method of dual damascene structure
  • Formation method of dual damascene structure
  • Formation method of dual damascene structure

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Embodiment Construction

[0037] As mentioned in the background art, the inner wall of the double damascene structure formed in the prior art is not smooth enough, which affects the performance of the subsequently formed metal interconnection structure.

[0038] The study found that due to the via-first dual-damascene process, it is necessary to form a via structure with a large aspect ratio in the dielectric layer first. Due to the large depth of the through hole, in the subsequent process of removing the bottom anti-reflection layer filling the through hole, more etching gas is exposed above the through hole, and the etching rate is relatively high, which will cause damage to the dielectric layer. A certain amount of etching, but less etching gas enters the lower part of the through hole, which will cause a certain residue of the anti-reflection layer at the bottom, making the inner wall of the double damascene structure uneven, resulting in the formation of voids in the subsequent filling of the meta...

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Abstract

The invention provides a formation method of a dual damascene structure. The formation method of the dual damascene structure comprises the steps of providing a substrate, forming a dielectric layer on the surface of the substrate, forming a through hole in the dielectric layer, forming a bottom antireflection layer in the through hole in such a manner that the through hole is full of the bottom antireflection layer and the surface of the dielectric layer is covered, forming, on the surface of the bottom antireflection layer, a mask layer with an opening which is located above the through hole in position and exposes partial surface of the bottom antireflection layer, removing the partial bottom antireflection layer which is located on the surface of the dielectric layer under the opening and exposing the surface of partial dielectric layer and the surface of the bottom antireflection layer in the through hole, etching the dielectric layer and the bottom antireflection layer in the through hole along the opening to form a first groove, removing the rest bottom antireflection layer in the through hole, and etching the dielectric layer along the first groove to form a second groove. The formation method is capable of improving the flatness of the inner wall of the damascene structure.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a double damascene structure. Background technique [0002] With the development of semiconductor technology, the chip integration level of VLSI has reached hundreds of millions or even billions of devices, and multi-layer metal interconnection technology with more than two layers is widely used. Traditional metal interconnects are made of aluminum metal, but with the continuous reduction of device feature size in integrated circuit chips, the circuit density in metal interconnect lines continues to increase, and the required response time continues to decrease. Traditional aluminum Interconnect lines are no longer adequate. After the process size is less than 130 nanometers, copper interconnection technology has replaced aluminum interconnection technology. Compared with aluminum, the lower resistivity of metallic copper can reduce the resistance-ca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76808
Inventor 黄瑞轩王冬江
Owner SEMICON MFG INT (SHANGHAI) CORP
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