Anti-interference circuit and storage element of static random access memory unit

Abstract

The invention discloses an anti-interference circuit and a storage element of a static random access memory (SRAM) unit. The anti-interference circuit of the static random access memory unit comprises a first switch element and a capacitor which are connected in series and are respectively connected to storage nodes (Q, QB) of the static random access memory unit, the first switch element is controlled by a first word line (WLB), the first word line switches on and off the first switch element respectively during the period of read-write operation and keeping operation of the static random access memory unit. The anti-interference circuit has high anti-interference performance during the period of the keeping operation; in addition, when the SRAM unit reads and writes, the circumstance that the read-write speed slows down due to too many elements connected to the storage nodes is avoided.

Description

technical field [0001] The present invention relates to the technical field of static random access memory (SRAM), and more particularly, relates to an anti-interference circuit and a storage element of a static random access memory unit. Background technique [0002] According to the data storage method, semiconductor memory is divided into dynamic random access memory (DRAM), non-volatile memory and static random access memory (SRAM). SRAM has established its unique advantage by being able to achieve fast operating speeds in a simple and low power consumption manner. Also, compared to DRAM, SRAM is relatively easy to design and manufacture because it does not need to periodically refresh the stored information. [0003] Generally, an SRAM cell consists of two drive transistors, two load devices, and two access transistors. According to the type of load devices contained, SRAM itself can be divided into complete complementary metal-oxide-semiconductor (CMOS) SRAM, high loa...

AI Technical Summary

Problems solved by technology

However, due to the following disadvantages of the SRAM unit, it has not been widely used

First, there is a threshold voltage loss in a single NMOS or PMOS; figure 2 There is a voltage difference between the drains of M1 and M3, making the storage node susceptible to noise

Secondly, due to the delay caused by the addition of pass transistors on the critical path, the read and write speeds are very slow

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