A plc physical layer clock synchronization method
A physical layer clock and sampling clock technology, applied in the direction of synchronization devices, digital transmission systems, electrical components, etc., can solve problems such as loop problems, reception deterioration, instability, etc., to shorten networking time, increase robustness, and simplify The effect of maintenance
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[0012] A PLC physical layer clock synchronization method, the transmission signal of the physical layer is composed of a frame header modulated by known data OFDM and a frame body modulated by control data or upper layer data that needs to be transmitted, and inserted into the frame body The pilot signal modulated by known data OFDM; when the receiver processes the received signal of the frame header, it estimates the preliminary clock frequency and phase deviation; according to the estimated sampling clock error, the digital received signal is interpolated, so that the interpolation The sampling clock of the obtained digital received signal is synchronized with the digital signal of the transmitting end on the clock; when the receiver processes the received signal of the frame body part, the clock phase deviation is further estimated according to the pilot signal, and the interpolated parameters are calculated according to the estimated clock phase deviation Make adjustments. ...
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