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Semiconductor device preparation method

A semiconductor and device technology, which is applied in the field of semiconductor device preparation, can solve the problems of short-channel device characteristic degradation, increase short-channel effect, unfavorable ultra-shallow junction, etc., and achieve suppression of short-channel effect, reduction of leakage, and improvement of performance effect

Inactive Publication Date: 2015-01-07
FUDAN UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

During the subsequent annealing process and activation of semiconductor devices, EOR defects are difficult to be repaired by annealing, which causes serious problems: on the one hand, such EOR defects will enhance the diffusion of previously implanted germanium, boron (or BF2) ions, Increasing the short channel effect is not conducive to the formation of ultra-shallow junctions; on the other hand, the formed amorphous layer recrystallizes, and the EOR defects will dissolve the semiconductor interstitial atoms that effectively migrate to the surface of the device structure, which is easy to cause the transient enhanced diffusion effect (TED ), resulting in short-channel device characteristic degradation and greater junction leakage

Method used

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  • Semiconductor device preparation method
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Embodiment Construction

[0034] The method for preparing the semiconductor device of the present invention will be described in more detail below in conjunction with the schematic diagram, wherein a preferred embodiment of the present invention is represented, it should be understood that those skilled in the art can modify the present invention described here, and still realize the advantages of the present invention Effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0035] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals...

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Abstract

The invention provides a semiconductor device preparation method. A non-crystallizing region is formed in a semiconductor substrate, and then a source / drain region in a semiconductor device is formed in the non-crystallizing region. The non-crystallizing region can restrain generation of defects at the tail end of the source / drain region, and therefore electric leakage between the source / drain region and the semiconductor substrate of the semiconductor device can be well lowered; besides, after a virtual grid structure is removed, a short channel suppression region is formed in a channel region, the short channel effect of the semiconductor device can be suppressed, and the demand that the feature size of the device gradually decreases is met.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a semiconductor device. Background technique [0002] With the advancement of the semiconductor industry and the development of Moore's Law, the feature size and depth of MOS (metal oxide semiconductor) devices are shrinking, especially when entering the node of 65 nanometers and below, the channel of MOS devices is getting shorter and shorter. The effect (SCE) is getting more and more serious, and the source / drain DIBL (Inductive Barrier Lowering) leakage is serious. [0003] Due to the continuous shrinking of the feature size and depth, the source / drain region and the source / drain extension (Source / Drain Extension) are required to be correspondingly shallower, and the doped junction with a junction depth below 100nm is usually called an ultra-shallow junction ( USJ), the ultra-shallow junction can better improve the short-channel effect of the ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L29/66045H01L21/26506H01L21/26513H01L21/2658H01L29/6659H01L29/7833H01L29/66537H01L29/66545H01L29/665H01L29/1033H01L21/324
Inventor 吴东平许鹏周祥标付超超
Owner FUDAN UNIV