Folded-gated l-channel low-leakage current tunneling transistor

Abstract

The invention relates to a folded gate-controlled L-shaped channel low-leakage current tunneling transistor. The folded gate electrode structure design adopted can simultaneously control the horizontal and vertical parts of the L-shaped intrinsic silicon, combined with the L-shaped intrinsic silicon The silicon structure design, on the one hand, ensures that the device has a faster current rise rate in the subthreshold region and enhances the forward conduction capability; on the other hand, it significantly slows down the energy band bending near the drain region of the device in the reverse bias state, so Compared with ordinary tunneling transistors, the present invention not only ensures that the device has better forward characteristics, but also enables the device to have the advantages of lower reverse leakage current and lower static power consumption; in addition, the present invention also provides The specific manufacturing method of the structural unit of the device is clarified, so it is suitable for popularization and application.

Description

technical field [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a specific structural unit and a manufacturing method of a folded gate-controlled L-shaped channel low-leakage current tunneling transistor suitable for ultra-high-integrated integrated circuit manufacturing. Background technique [0002] Currently, silicon-based PIN-type tunneling field-effect transistors (referred to as tunneling transistors) have the potential to achieve better switching characteristics and lower power consumption compared with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs). , so it can replace MOSFETs and become one of the basic unit candidates of the new generation of integrated circuits. The disadvantage of the current tunneling transistor manufactured according to the existing technology is that the gate electrode voltage can generate a considerable tunneling current when it is forward-biased and rev...

AI Technical Summary

Problems solved by technology

The disadvantage of the current tunneling transistor manufactured according to the existing technology is that the gate electrode voltage can generate a considerable tunneling current when it is forward-biased and reverse-biased, which makes the static power consumption of the tunneling transistor larger. At the same time, Tunneling transistors manufactured by existing planar technology are similar to MOSFETs. When the channel length of the device is too short, the subthreshold characteristics decrease due to the weakening of the gate electrode control ability and the channel voltage caused by the drain voltage. Dow barrier lowering effect (DIBL) and other issues

[0003] Increasing the dielectric constant of the gate insulating layer can enhance the control ability of the gate electrode to short-channel TFETs devices, improve subthreshold characteristics and solve problems such as DIBL. The problem of generating a large tunneling current, so instead of reducing but increasing the static power consumption of the tunneling transistor

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