Universal floating point matrix processor hardware structure based on FPGA (field programmable gate array)

A hardware structure and floating-point matrix technology, applied in the architecture with a single central processing unit, general-purpose stored program computer, climate sustainability, etc., can solve the problems of waste of computing resources, increase the workload of the main processor, etc., to achieve The effect of high computing performance, high design flexibility, and low energy consumption

Active Publication Date: 2015-03-04
TSINGHUA UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Continuous status checking increases the workload of the main processor, while the gap between the main p

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  • Universal floating point matrix processor hardware structure based on FPGA (field programmable gate array)
  • Universal floating point matrix processor hardware structure based on FPGA (field programmable gate array)
  • Universal floating point matrix processor hardware structure based on FPGA (field programmable gate array)

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Embodiment Construction

[0032] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0034] In the present invention, unless otherwise clearly specified...

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Abstract

The invention discloses a universal floating point matrix processor hardware structure based on an FPGA (field programmable gate array). The universal floating point matrix processor hardware structure comprises a plurality of matrix operation accelerators, a plurality of shared matrix buffer memories, a main processor, an instruction dispatcher, a direct access controller, an arbiter, an external memory and a memory management unit, the shared matrix buffer memories provide universal memory spaces and support high-speed communication on chips between the accelerators, the main processor transmits instructions, dispatches operation and calculates addresses, the instruction dispatcher inspects whether the instructions have occupying conflict or not, the direct access controller finishes data transmission, the arbiter distributes data, the external memory provides buffer, and the memory management unit provides an access interface. The hardware structure can realize 'matrix-matrix' operation on a universal platform, software programs can be modified on the main processor according to different applications, a matrix operation accelerator structure can be conveniently inserted to support various matrix operations, the universal floating point matrix processor hardware structure has high design flexibility and has the advantages of lower energy consumption and higher calculated performance as compared with an embedded processor performing the matrix operations in the past.

Description

technical field [0001] The invention relates to the technical fields of computers and electronic information, in particular to a general floating-point matrix processor hardware structure based on FPGA (Field-Programmable Gate Array, Field Programmable Gate Array). Background technique [0002] In recent years, mobile working platforms such as drones and mobile robots have become one of the research hotspots. These devices have high flexibility and are widely used in disaster relief, geological survey and other scenarios. A large number of matrix operations are required in the application of the mobile work platform, which has high requirements on the speed and power consumption of matrix operations. For example, the Kalman filter is a method widely used in mobile robot localization, and its operation process includes a series of matrix operations. In order to ensure the real-time positioning of the robot, these matrix operations need to be performed at high speed; at the ...

Claims

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Application Information

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IPC IPC(8): G06F15/78
CPCY02D10/00
Inventor 谷梦媛王文强汪玉郭开元杨华中
Owner TSINGHUA UNIV
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