Gate structure of separation gate power device and process method

Abstract

The invention discloses a gate structure of a separation gate power device. A silicon substrate is provided with a trench. The side walls and the bottom of the trench are each provided with an oxide layer in an attachment mode. The lower portion in the trench is provided with a separation gate. The upper portion of the separation gate is covered with a silicon oxide layer as well. The silicon oxide layer on the separation gate and the silicon oxide layers on the side walls and at the bottom of the trench encircle the separation gate. The upper portion of the trench is a gate. The surface of the silicon substrate is an insulating layer. A metal lead penetrates through a contact hole of the insulating layer and leads the gate out. The gate is a polycrystalline silicon thin gate of a U-shaped structure and filled with metal tungsten, and the contact hole is connected with the filled metal tungsten to lead the gate out. The invention further discloses a process method of the gate structure of the separation gate power device.

Description

technical field [0001] The invention relates to the field of design and manufacture of integrated circuits, in particular to a gate structure of a split gate power device, and also relates to a process method for the gate structure. Background technique [0002] At present, power semiconductor devices using a split gate structure use polysilicon materials for the gate, such as figure 1 As shown, it is a schematic cross-sectional view of a split gate structure. The gate is a trench type. A gate oxide layer is deposited on the inner wall of the trench and then filled with polysilicon. The lower part has a split gate 5 and the upper part has a polysilicon gate 6 . [0003] Polysilicon needs to be filled into holes (or trenches), and it is well known that polysilicon has a relatively poor hole-filling ability. holes will be formed, such as figure 2 (A cross-sectional micrograph of a trenched polysilicon gate) is circled. Even if there is no hole, a closed line will be formed...

AI Technical Summary

Problems solved by technology

Removing excess silicon requires an etching process. There are many options, such as dry etching, wet etching, chemical mechanical polishing, etc., but because of the existence of holes or closed lines, the center of the polysilicon gate will be etched faster without exception, forming pits, such as image 3 shown

In extreme cases, it will lead to punch-through or reduced reliability

If the design needs to make leads here, it will double the deterioration

[0005] In addition, the polysilicon gate process adopts a furnace tube process, including first growing 1.2 μm in a furnace tube at 538°C, and then performing photolithography, dry etching, etc., which has high cost, long time, many defects, and complicated process

The thermal process leads to the diffusion of impurity atoms in the substrate, which reduces the performance of the product

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