A current signal demodulation circuit

Abstract

The invention discloses a current signal demodulation circuit, which is characterized in that it comprises: an inductance edge sampling circuit, a comparison amplifier circuit and a feedback maintenance circuit, the current passing through each slave station S1S2...SN passes through the aforementioned inductance edge sampling circuit to form a loop, The aforementioned inductance edge sampling circuit samples the rising edge and falling edge of the changing current on the bus, and the obtained sample signal is first compared and amplified in the aforementioned comparison amplifier circuit, and the aforementioned feedback maintenance circuit feeds back the output of the latter stage to the comparator in the comparison amplifier circuit The input terminal maintains the output level of the comparator during the disappearance of the sampling signal, and sets the flipping threshold. The advantages of the present invention are: it has a relatively high communication rate range and strong anti-interference ability; it can reliably receive in a large current dynamic range, so that a large load can be mounted on the bus; it can reduce sampling power consumption and adapt to The battery-powered environment and solar-powered environment are conducive to product miniaturization; they can simplify product structure and reduce costs.

Description

technical field [0001] The invention relates to a circuit, in particular to a current signal demodulation circuit, belonging to the technical field of electricity. Background technique [0002] The current master station demodulation circuit, its working principle is as follows: figure 1 As shown, from the bus BUS1 flows through the slave station S1, slave station S2, ..., slave station S N The current signal arriving at the bus BUS2 is sampled by the sampling resistor R1, and coupled to the lower circuit after the DC signal is removed by the coupling capacitor C1. [0003] There are three main problems with this circuit: [0004] 1. There is a problem of working point drift, and it cannot work normally under heavy load dynamic conditions. [0005] For example: if the sampling resistance is 1 ohm, the current of the bus empty signal is 100mA, a 100mV reference voltage is generated on the sampling resistor, and the mark sampling voltage is 110mV; and when the space current...

AI Technical Summary

Problems solved by technology

[0004] 1. There is a problem of working point drift, and it cannot work normally under large load dynamic conditions

[0005] For example: if the sampling resistance is 1 ohm, the current of the bus empty signal is 100mA, a 100mV reference voltage is generated on the sampling resistor, and the mark sampling voltage is 110mV; and when the space current rises to 3A, the voltage obtained by the sampling resistor is 3V, and the mark sampling voltage is 110mV. The sampling voltage is 3.01V, the operating point drifts a lot, and it is difficult to detect the signal

[0006] 2. Since the signals during the entire current change period need to be capacitively coupled, the adaptability of the communication rate range is poor

[0007] Generally speaking, the bus communication requires normal operation from 300bps to 9.6Kbps. Under the asynchronous communication conditions of 8 data bits, 1 start bit, 1 check bit, and 1 stop bit, the signal detection requirement is extended to 27Hz To 9.6KHz, the frequency range is large, and the circuit ratio is very difficult; moreover, in the case of unbalanced distribution of communication frames 0 and 1, the charging and discharging of the coupling capacitor is even more insufficient, which will directly lead to the signal of the last byte of the frame Distortion, unable to restore the signal

[0008] 3. As the load current increases, the power consumption of the sampling resistor R1 increases, resulting in severe heating of the circuit, so the number of nodes that can be connected is small

Images