Digital fractional frequency division phase-locked loop control method and phase-locked loop

A technology of fractional frequency division and phase-locked loop, applied in the field of electronics

Active Publication Date: 2017-03-08
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is usually a relatively close compromise between range and accuracy, and it is often difficult to meet the requirements of the above two dimensions at the same time
Due to the limitations of the structure of the TDC itself, in order to meet the above requirements, the design of the TDC poses a very big challenge

Method used

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  • Digital fractional frequency division phase-locked loop control method and phase-locked loop
  • Digital fractional frequency division phase-locked loop control method and phase-locked loop
  • Digital fractional frequency division phase-locked loop control method and phase-locked loop

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Embodiment Construction

[0086] image 3 A schematic structural diagram of a digital fractional frequency-division phase-locked loop provided in Embodiment 1 of the present invention, as shown in image 3 As shown, the phase-locked loop includes a control device and a time-to-digital converter TDC, a digital loop filter DLF, a digitally controlled oscillator DCO, a feedback frequency divider DIV and a Sigma-Delta modulator SDM.

[0087] Wherein, the output end of the control device is connected to the first input end of the TDC; the output end of the TDC is connected to the input end of the DLF, the output end of the DLF is connected to the input end of the DCO, and the output end of the DCO is connected to the first input end of the DIV ; The output end of DIV is connected with the second input end of TDC; The second input end of DIV is connected with the output end of SDM, the first input end of the control device is connected with the output end of SDM, the second input end of the control device is...

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Abstract

Embodiments of the present invention provide a digital fractional frequency division phase-locked loop control method and a phase-locked loop. The phase-locked loop includes a control device, TDC, DLF, DCO, DIV, and SDM. The effective edge of the reference clock is delayed to obtain the delayed reference clock; the delayed reference clock is sent to the TDC so that the TDC performs phase detection processing on the delayed reference clock and the feedback clock. The control device added in the phase-locked loop can delay the reference clock according to the current frequency control word and the frequency division control word, so that the feedback clock and the delayed reference clock have similar effective edge corresponding times, so that TDC only needs to process a small amount of time The phase detection signal in the domain input range greatly reduces the difficulty of TDC design and the demand for TDC resolution, making the design of TDC simple and free, thus ensuring the freedom of design of the phase-locked loop and being simple and effective.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a digital fractional frequency division phase-locked loop control method and the phase-locked loop. Background technique [0002] In radio frequency transceivers, a frequency synthesizer based on a Phase-Locked Loop (PLL) structure is widely used to generate a local oscillator signal, referred to as a local oscillator signal, to complete a frequency shift operation of a data signal. [0003] In a wireless communication system, especially in a wireless terminal, due to factors such as cost, a Zero Intermediate-Frequency (ZIF) radio frequency transceiver architecture is widely used. In a radio frequency transceiver of this type of architecture, no matter it is a signal transmitting channel or a signal receiving channel, it is required that the frequency of the local oscillator signal is exactly the same as that of the radio frequency carrier frequency signal. That ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/18
CPCH03L7/085H03L7/1976H03L7/081H03L7/091H03L7/0992H03L7/1974
Inventor 高鹏
Owner HUAWEI TECH CO LTD
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