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mos transistor with reduced leakage well substrate junction

A MOS transistor and transistor technology, applied in the field of doping arrangement, can solve problems such as Ioff increase

Active Publication Date: 2019-08-09
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Using a lower power supply level forces V t decrease, which can cause a significant increase in Ioff

Method used

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  • mos transistor with reduced leakage well substrate junction
  • mos transistor with reduced leakage well substrate junction
  • mos transistor with reduced leakage well substrate junction

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Experimental program
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Embodiment Construction

[0013] figure 1 is a flowchart illustrating the steps of an exemplary method 100 comprising at least one high Energy implants to add doped regions below the junctions for forming MOS transistors with reduced leakage well-substrate junctions. Reduces well-substrate junction leakage by increasing substrate surface doping between the bottom of the well-depleted region and one diffusion length out of the well-depleted region, thereby reducing the minority carrier doping level without significant Change the electrical characteristics of the devices in the well (including the V of the MOS device in the well) t and junction capacitance). Typical values ​​for one diffusion length of the well-substrate junction may be 5-20 μm.

[0014] Step 101 includes forming a well doped with a second dopant type on a semiconductor surface doped with a first dopant type having a baseline doping level, wherein the well forms a well-substrate junction. The well can be an n-well and the semiconduct...

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Abstract

A metal oxide semiconductor (MOS) transistor (340) includes a substrate (105) having a topside semiconductor surface (106) doped with a first dopant type having a baseline doping level. A well (210) is formed in the semiconductor surface doped with the second doping type. The well forms a well-substrate junction with a well depletion region (215). A doped region (220) below the well-substrate junction is doped with the first dopant type and has a doping level between 5-100 times higher than the baseline doping level at the location of the peak first dopant concentration A peak first dopant concentration wherein at least 90% of the total dose of the doped region is below the bottom of the well depletion region with zero bias across the well substrate junction. Gate structures (341, 342) are on the well. A source region (344) and a drain region (345) are on opposite sides of the gate structure.

Description

technical field [0001] The invention relates to a semiconductor device comprising an integrated circuit with a pn junction comprising a doping arrangement for reducing pn junction leakage. Background technique [0002] Leakage current has become a significant contributor to the standby power consumption of complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) and is usually measured at the transistor level by the transistor parameter off-state current (Ioff). Ioff is the drain current when the applied gate voltage is zero with a certain drain-to-source voltage (Vdd) applied. [0003] Ioff is affected by the threshold voltage of the device (V t ), channel physical dimensions, channel / surface doping profile, drain / source junction depth, gate dielectric thickness, and Vdd. Ioff in long-channel devices is known to be controlled by reverse bias leakage from the drain-well and well-substrate junctions. Short-channel transistors generally require lower power s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L27/1214H01L29/06H01L29/0607H01L29/66477H01L29/78H01L21/26513H01L21/823892H01L27/092H01L27/0921H01L29/1083H01L29/6659H01L29/7833
Inventor T·J·伯德伦A·查特吉
Owner TEXAS INSTR INC