A method of making embedded split-gate flash memory gate

Abstract

The invention discloses a method for manufacturing embedded split-gate type flash memory gate. According to the method of the invention, a hard mask layer is deposited on the wafer before patterning the polysilicon layer in the logic circuit area to solve the problem of subsequent bit lines. and the damage to the polysilicon layer in the logic circuit area during the etching step of the polysilicon layer in the logic circuit area, so as to improve the overall performance of the embedded split-gate flash memory and the yield rate of the embedded split-gate flash memory.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a manufacturing method of an embedded split-gate type flash memory gate. Background technique [0002] Memory is used to store a large amount of digital information. According to recent surveys, memory chips account for about 30% of semiconductor transactions worldwide. Over the years, technological progress and market demand have led to more and more high-density various Types of memory, such as RAM (random access memory), SRAM (static random access memory), DRAM (dynamic random access memory) and FRAM (ferroelectric memory), etc. [0003] Random access memory, such as DRAM and SRAM, has the problem of data loss after power failure during use. To overcome this problem, various nonvolatile memories have been designed and developed. Recently, flash memory based on the floating gate concept has become the most versatile non-volatile memory due to its small cell size and go...

AI Technical Summary

Problems solved by technology

Since the thickness of the polysilicon layer in the logic circuit area is several hundred angstroms smaller than the polysilicon layer in the flash memory cell area (flash word line area), when the polysilicon layer in the two areas is etched simultaneously, the polysilicon layer in the logic circuit area More polysilicon layer is over-etched, which will make the device performance mismatch between embedded logic gates and non-embedded logic gates, while analyzing the embedded logic from the results of TEM (Transmission Electron Microscopy) and electronic testing The performance of the gate is degraded, which will affect the performance of the entire integrated circuit

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