Shur algorithm-based interpolation filter applied to full-digital receiver

Abstract

The invention discloses a shur algorithm-based interpolation filter applied to a full-digital receiver. The shur algorithm-based interpolation filter comprises a plurality of filter units, wherein each filter unit comprises a first summator, a first multiplier and a plurality of sub units, the number of the sub units in the filter units is equal to that of the filter units included by the interpolation filter, the output end of the final sub unit is connected with the first input end of the first summator, the second input end of the first summator inputs an interpolation estimated value, the output end of the first summator is connected with the input end of the first multiplier, and the other input end of the first multiplier inputs an interpolation estimated value. According to the shur algorithm-based interpolation filter, an interpolation filter algorithm is mapped into a VLSI structure, and a conventional DSP realizing method is replaced, so that the problems of difficulty in massive data processing and low processing speed are solved; a lattice structure of the interpolation filter is deduced by using a Schur algorithm, so that a vertex and a null point of a transmission function are relatively sensitive to a coefficient of the quantized first multiplier, therefore, the sensitivity is improved.

Description

technical field [0001] The invention relates to an interpolation filter, in particular to an interpolation filter based on a shur algorithm applied to an all-digital receiver. Background technique [0002] With the development of the communication industry, a demodulation technology of a digital open-loop structure without a phase-locked loop or a feedback loop has attracted people's attention. This is the all-digital receiver technology. The all-digital receiver uses a digital-to-analog converter to sample and quantize the modulated carrier signal received by the receiver at the front end of the receiver, that is, at the intermediate frequency, high frequency or near the receiving antenna, and converts it into a digital signal. The subsequent functions of the receiver are all used Digital processing technology is realized. [0003] In digital communication, symbol synchronization and carrier synchronization are the key technologies of the receiver. In a common digital com...

AI Technical Summary

Problems solved by technology

[0006] 1. With the improvement of modern integrated circuit technology, although the performance of modern DSP processors is very high, it is still difficult for a single-chip DSP to process very high signals, and cannot adapt to high-speed electronic technology design

[0007] 2. Even if the digital receiver of the intermediate frequency band undergoes A / D conversion, the output data is all realized by software, and the amount of calculation is very large, and such a large calculation is difficult to operate in real time

Therefore, DSP is the "bottleneck" of realization in the case of real-time operation and large amount of computation

[0008] 3. The DDS realized by DSP is rich in spurious components, and the output frequency band is limited

[0011] 1. Although C.W.Farrow proposed that the Farrow structure greatly simplifies the difficulty of hardware implementation, the running speed of the interpolation filter realized is not satisfactory compared with the present invention

The critical path of the interpolation filter implemented with this structure is long, and parallel signal processing is not implemented, which makes the system running speed unable to be further improved, and does not meet the growing demand of modern electronic products for low speed

[0012] 2. Another problem brought about by the easy-to-implement Farrow structure is power consumption

The power consumption of the interpolation filter realized by the Farrow structure is higher than that of the present invention, and does not meet the low power consumption requirements that modern electronic products are increasingly pursuing.

[0013] 3. The Farrow structure interpolation filter does not achieve satisfactory results for 64QAM, 256QAM and other high-efficiency modulation signals

[0014] 4. Although the selection of interpolation filter parameters realized by the Farrow structure of the Lagrangian cubic interpolation filter has been improved, the Farrow structure of the Lagrange cubic interpolation filter has not changed, and only some accuracy and bit errors can be solved. The problem of efficiency, failed to effectively improve the system speed and reduce the power consumption of the system

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