A delay adjustment circuit with adjustable range and step size

Abstract

The present invention discloses a range-adjustable, and step length adjustable delay adjustment circuit, which includes an input buffer, used to adjust a swing of an input signal, wherein an input of the input buffer is a two-path differential signal, an output is a signal suitable for a working range of a delay kernel, and the delay kernel generates a DC level according to an input bias current, and determines the size of the delay according to the position of an intersection point of the DC level and an edge; a comparator, used to compare the edge of the signal output by the delay kernel with the DC Level and determine an output reversal position according to the intersection point; an output buffer, used to delay the input original signal and output the delayed signal; a NOR gate, being responsible for performing overlapping processing on the delayed signal and the original signal; and an RS trigger, used to restore the input pulse signal as a square wave signal. The range adjustable, and step length adjustable delay adjustment circuit of the present invention has a good linearity characteristic, can adjust the delay range of the signal, and can adjust the step length of the delay with a minimum step length of 8 p; moreover, the output delay varies with the voltage and temperature of the power supply in a small amount.

Description

technical field [0001] The invention relates to a delay adjustment circuit, in particular to a delay adjustment circuit with adjustable range and adjustable step length. Background technique [0002] The rapid development of integrated circuit design technology, especially after the design of integrated circuits has entered the sub-micron and deep sub-micron levels, the operating frequency, circuit area, wiring level and integration of integrated circuits have been continuously improved, making circuit interconnection an important factor affecting circuit design. an important factor. [0003] To achieve a certain delay in circuit design, a corresponding delay circuit is required. The traditional delay adjustment circuit is generally formed by cascading inverters, and is mainly adjusted by the charging capacity of the PMOS transistor and the discharging capacity of the NMOS transistor. The minimum delay time is determined by the number of cascaded inverters to determine the ...

AI Technical Summary

Problems solved by technology

Due to the limitation of the charging and discharging ability of the inverter itself, the minimum resolution is generally greater than 30p, and with the change of temperature and power supply voltage, its flipping threshold will change, and the delay time will also change accordingly.

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