MOS transistor circuit having gate bias compensation
A technology of MOS transistors and transistors, applied in circuits, logic circuits, electrical components, etc., can solve problems such as greater impact on circuit performance, and achieve the effect of reducing power loss
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Embodiment 1
[0038] see figure 2 Schematic diagram of Embodiment 1 of the MOS transistor circuit with gate bias compensation of the present invention.
[0039] The MOS transistor circuit includes: a resistor element, a first NMOS transistor and a second NMOS transistor, wherein the resistor element is connected in series with the first NMOS transistor, and the second NMOS transistor is connected to the resistor element and the second NMOS transistor through a gate. An NMOS transistor is connected. Specifically, the gate of the first NMOS transistor and one end of the resistor element are connected to the power supply voltage, the sources of the first NMOS transistor and the second NMOS transistor are grounded, and the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor pole and the other end of the resistor element, and the drain of the second NMOS transistor is connected to the current output end.
[0040] Such as figure 2 As shown, M0 is the sec...
Embodiment 2
[0052] see image 3 Schematic diagram of Embodiment 2 of the MOS transistor circuit with gate bias compensation of the present invention.
[0053] Different from Embodiment 1, this embodiment adds a PMOS transistor with switching function. The MOS transistor circuit includes: a resistor element, a first NMOS transistor, a second NMOS transistor and a PMOS transistor, wherein the resistor element, the PMOS transistor and the first NMOS transistor are connected in series, and the second NMOS transistor is connected to the first NMOS transistor through a gate. The resistor element is connected to the first NMOS transistor. Specifically, the gate of the first NMOS transistor and the source of the PMOS transistor are connected to the power supply voltage, the sources of the first NMOS transistor and the second NMOS transistor are grounded, and the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor and One end of the resistor element, the dra...
Embodiment 3
[0056] see Figure 4 A schematic diagram of Embodiment 3 of the MOS transistor circuit with gate bias compensation of the present invention.
[0057]The MOS transistor circuit includes: a resistor element, a first PMOS transistor and a second PMOS transistor, wherein the resistor element is connected in series with the first PMOS transistor, and the second PMOS transistor is connected to the resistor element and the second PMOS transistor through a gate. A PMOS transistor is connected. Specifically, the gate of the first PMOS transistor and one end of the resistor element are grounded, the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage, and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor pole and the other end of the resistor element, and the drain of the second PMOS transistor is connected to the current output end.
[0058] Such as Figure 4 As shown, M4 is the fir...
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