IP (internet protocol) core of programmable spacecraft control engine

Abstract

The invention discloses an IP (internet protocol) core of a programmable spacecraft control engine. The IP core comprises a first on-chip peripheral; a first DMA (direct memory access) channel; a uniform handling engine pile capable of generating every motor control signal of a spacecraft according to triaxial accelerated velocity of the spacecraft, triaxial angular velocity of the spacecraft, GPS (global position system) data, space measuring data, spacecraft control data, first PID parameter and second PID parameter, and transmitting the signal to the spacecraft through the second DMA channel and a second on-chip peripheral; The IP core adopts a hardware system framework with a super assembly line and an ultra-long instruction set framework; through the hardware method, gesture and course of the spacecraft are controlled; a special optimized hardware greatly reduces the control delay.

Description

technical field [0001] The invention relates to the field of aircraft control, in particular to a programmable aircraft control engine IP core. Background technique [0002] When the aircraft is running, in order to complete the tasks it undertakes, it must have a certain control system. For example, when the quadrotor is hovering, it is necessary to control the aircraft to complete the flight in the specified direction and specified attitude through the control system. For the aircraft, not only attitude control and correction, but also other control actions such as heading correction are required to ensure that the aircraft flies in the desired manner. [0003] The aircraft control system in the prior art generally adopts a general-purpose CPU+general-purpose A / D sampling+general-purpose D / A output architecture, which is simple in design, and the general-purpose CPU is the same as the existing programming model. Using this method means that the general-purpose CPU needs t...

AI Technical Summary

Problems solved by technology

Using this method means that the general-purpose CPU needs to perform attitude control, heading control and other operations at all times. For general embedded processors, this calculation is very large, and the processor often cannot be redistributed to other applications, making some The design and architecture have to use more than two general-purpose CPUs, one of which is used for attitude control and the other is used to implement airborne applications; at the same time, for the aircraft control process, its data path has obvious producer-consumer data characteristics , the existing general-purpose CPU can’t process these data streams in parallel for control-intensive applications, so the processing efficiency of the whole system is greatly reduced; the attitude control system in the prior art still has a part of the design of general-purpose CPU+hardware PID, This design can only relieve the calculation pressure of the PID part, and has little effect on improving the entire aircraft control system

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