Thin film transistor and manufacturing method thereof as well as array substrate and display device

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a thin film transistor and a manufacturing method thereof as well as an array substrate and a display device. A source electrode and a drain electrode of the thin film transistor are located on an active layer, the whole active layer is located on a same plane, the problem that a wire of the active layer is easy to break due to climbing difficulty in the prior art is solved, the thickness of the active layer is uniform, the breakdown short circuit phenomenon cannot occur, and the yield of the thin film transistor is improved. The source electrode and the drain electrode are arranged to be in a different layer structure, the distance between the source electrode and the drain electrode can be flexibly adjusted, a narrow channel is easy to realize, and the performance of the thin film transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor device preparation, in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. Background technique [0002] combine figure 1 and figure 2 As shown, in a coplanar thin film transistor (Thin Film Transistor, TFT for short), the source electrode 3 , the drain electrode 4 and the gate electrode 1 are all disposed on the same side of the active layer 2 . According to the position of the gate electrode 1 relative to the active layer 2, coplanar TFTs are classified into top-gate coplanar TFTs (combined figure 1 shown) and bottom-gate coplanar TFT (combined figure 2 shown). [0003] Thin Film Transistor Liquid Crystal Display (TFT-LCD for short) has the characteristics of small size, low power consumption, no radiation, and relatively low manufacturing cost, and occupies a dominant position in the current flat panel display market. Wh...

AI Technical Summary

Problems solved by technology

When coplanar TFT is used in TFT-LCD, for top gate coplanar TFT, such as figure 1 As shown, the pixel electrode 5 is in electrical contact with the drain electrode 4 through the via hole penetrating the passivation layer 102 and the gate insulating layer 101. Since the depth of the via hole is too large, it is difficult to climb the slope, and the pixel electrode 5 is easily disconnected, causing electrical contact. poor sexual contact

However, if the electrical connection between the pixel electrode 5 and the drain electrode 4 is realized in the form of a jumper, the number of Masks will be increased, and the production cost will be increased.

For the bottom gate coplanar TFT, such as figure 2 As shown, the active layer 2 overlaps the source electrode 3 and the drain electrode 4, and the etching process for forming the source electrode 3 and the drain electrode 4 results in rough sides of the source and drain metal. Since the thickness of the active layer 2 is very thin, when When it is lapped on the source electrode 3 and the drain electrode 4, the sides of the source electrode 3 and the drain electrode 4 are rough and climb, which makes the active layer 2 easy to break, and the thickness is uneven, and it is easy to shock during the power-on process. short circuit

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