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Forming method of storage

A memory and graphics technology, applied in the manufacture of electric solid-state devices, semiconductor devices, semiconductor/solid-state devices, etc., can solve the problems of poor charge storage capacity of floating gates, achieve high flatness, improve the ability to hold charges, and uniform thickness Effect

Active Publication Date: 2015-07-01
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

[0004] With the shrinking of the semiconductor feature size, the thickness of the insulating layer in ETOX continues to decrease, and the local electric field strength near the insulating layer is often greater than the surrounding electric field strength, which makes the ability of the floating gate to store charges worse. At present, there is an urgent need for a memory The formation method, without increasing the thickness of the insulating layer, reduces the local electric field strength near the memory, so as to improve the ability of the floating gate to store charges

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Embodiment Construction

[0032] With the shrinking of the semiconductor feature size, the thickness of the insulating layer in the memory, especially in ETOX, is constantly decreasing. It often occurs that the local electric field strength near the insulating layer is greater than the surrounding electric field strength, which makes the ability of the floating gate to hold charges worse.

[0033] The phenomenon that the local electric field intensity near the insulating layer of the existing technology is greater than the intensity of the surrounding electric field is analyzed. The uniformity is poor, causing the local electric field strength near the insulating layer to be greater than that of the surrounding electric field.

[0034] In order to solve the technical problem, the present invention provides a method for forming a memory, using a self-aligned isolation structure process, after forming the floating gate and the isolation material layer between the floating gates, the top of the floating ga...

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Abstract

The invention provides a forming method of a storage. The forming method includes providing a substrate; forming a floating gate material layer on the substrate; imaging the floating gate material layer and the substrate, and forming floating gates on the substrate and an opening formed in the substrate positioned between the floating gates; forming an isolation material layer in the opening; performing first chemical and mechanical lapping on the tops of the floating gates and the top of the isolation material layer, to planarize the upper surfaces of the floating fates; removing the isolation material layer between the gloating gates, thus allowing the isolation material layer in the substrate to form an isolation structure; forming an insulating layer on the side walls and upper surfaces of the floating gate and the surface of the isolation structure. As the upper surfaces of the floating gates are high in evenness, the insulating layer formed on the upper surfaces of the floating gates are uniform in thickness, sand thereby the local electric field intensity adjacent to the insulating layer is close to the electric field intensity of other areas, and the electric charge maintaining capacity of the floating gates can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a memory. Background technique [0002] With the development of the times, the storage of information is becoming more and more important. Non-volatile memory is a more commonly used information memory, which stores 0 / 1 information by storing charges on the floating gate. The non-volatile memory can also resist magnetic interference well when there is no electricity to maintain it, so the non-volatile memory is widely used. [0003] Tunnel oxide layer non-volatile memory (Eprom Tannel Oxide, ETOX) is a more commonly used non-volatile memory. ETOX includes control gate, floating gate, gate oxide layer of floating gate, control gate floating gate insulating layer and source region , Drain region, by applying a voltage to the control gate, the electrons in the source region reach the floating gate under the effect of tunnel effect to realize the write op...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H10B41/30
CPCH10B41/00
Inventor 邹陆军李绍彬仇圣棻
Owner SEMICON MFG INT (SHANGHAI) CORP
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