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A test structure and its manufacturing method

A technology for testing structures and manufacturing methods, applied in the testing of single semiconductor devices, electrical components, electrical solid devices, etc., can solve problems such as the absence of metal gates

Active Publication Date: 2018-02-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, to obtain the capacitance-voltage curve, a corresponding test structure must be available; in the prior art, there is no test structure that can be used to obtain the work function of the metal gate of the high-k metal gate fin field effect transistor

Method used

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  • A test structure and its manufacturing method
  • A test structure and its manufacturing method
  • A test structure and its manufacturing method

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0047] Below, refer to Figure 1A-Figure 1K with figure 2 The detailed steps of an exemplary method of the semiconductor device manufacturing method proposed by the embodiment of the present invention will be described. Figure 1A-Figure 1K It is a schematic diagram of the graphics formed in the key steps of the manufacturing method of a test structure according to the embodiment of the present invention; wherein, Figure 1A -1, 1B-1, 1C-1, 1D-1, 1E-1, 1F-1, 1G-1, 1H-1, 1I-1, 1J-1 and 1K-1 are top views, Figure 1A-2 , 1B-2, 1C-2, 1D-2, 1E-2, 1F-2, 1G-2, 1H-2, 1I-2, 1J-2 and 1K-2 are corresponding top views and sectional views along line XX' ; figure 2 It is a typical flowchart of a manufacturing method of a test structure according to an embodiment of the present invention.

[0048] The manufacturing method of the test structure of the present embodiment comprises the following steps:

[0049] Step A1: Provide a compound semiconductor substrate including a first semico...

Embodiment 2

[0082] An embodiment of the present invention provides a test structure, which can be used to obtain the work function of a metal gate of a semiconductor device using a high-k metal gate fin field effect transistor. The test structure can be prepared by the method described in Example 1.

[0083] Below, refer to image 3 To introduce the test structure of this embodiment, where image 3 A is the top view of the test structure, image 3 B is along image 3 Sectional view of line XX' in A. Such as image 3 As shown, the test structure of this embodiment includes: a first semiconductor substrate 101, a second semiconductor substrate 102 located on the first semiconductor substrate 101, a high-k dielectric located on the second semiconductor substrate 102 An electrical layer 107 and a metal gate 108 located on the high-k dielectric layer, wherein the second semiconductor substrate 102 has at least one fin structure (Fin) 1022, and the high-k dielectric layer 107 covers The t...

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PUM

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Abstract

The invention provides a test structure and a manufacturing method thereof, which relate to the technical field of semiconductors. The method includes: S101: providing a first semiconductor substrate and a second semiconductor substrate thereon to form a hard mask layer; 102: patterning the hard mask layer, using the patterned hard mask layer to Etch the second semiconductor substrate to form trenches and fin structures between the trenches; S103: form shallow trench isolation in the trench; S104: remove a certain thickness of shallow trench isolation so that its height is lower than that of the fins type structure, and remove the part of the hard mask layer above the fin structure, and retain the part of the hard mask layer outside the area where the fin structure is located as an isolation structure; S105: form a covering fin structure between the isolation structures and Shallow trench isolation with high-k dielectric and metal gate. The method can conveniently prepare a test structure for testing CV curves. The test structure can easily measure the CV curve, and then obtain the work function of the metal gate.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a test structure and a manufacturing method thereof. Background technique [0002] In the field of semiconductor technology, with the continuous development of semiconductor technology, in order to obtain higher device density, performance and lower cost, the manufacture of semiconductor devices often adopts three-dimensional design, such as fin field effect transistor (finfield effect transistor, Hereinafter, it may be referred to as FinFET). In addition, in order to improve the performance of semiconductor devices, high-k metal gate technology has also begun to be more and more widely used. [0003] At present, more and more semiconductor manufacturers begin to use high-k metal gate technology and fin field effect transistor technology to manufacture semiconductor devices at the same time. In the manufactured semiconductor devices, the transistors used are high-k metal ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544G01R31/26
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP