First in first out storer circuit structure based on random access memory (RAM)

Abstract

The invention provides a first in first out storer circuit structure based on a random access memory (RAM) and relates to the field of chip design. A multi-input single-output FIFO structure body is established, a multi-access interface RAM storage body is established through at least three ordinary single-access interface RAM storage bodies, a configurable ranking mode is set, an independent read-write FIFO pointer is set, an FIFO upper overflowing error mark is achieved through a marked vector mark bit corresponding to an address in writing, and an FIFO lower overflowing error mark is output through an unmarked vector mark bit corresponding to the address in reading. By means of a novel FIFO structure, multi-channel message parallel writing FIFO can be directly achieved. Furthermore, automatic ranking can be achieved according to a set mode, serial can be output through FIFO, and a parallel storage function and a serial scheduling function can be automatically achieved.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a fast implementation method for parallel scheduling of data paths in the circuit implementation process of network control protocol chips in a multi-node network. Background technique [0002] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The realization of complex architecture supports high-end server systems to achieve high performance indicators, high security, high availability, and high reliability. This requires a network control chip to control the multi-processor system, so that the internal message transmission of the system can be efficient, reliable, safe and stable. For the design of this type of control chip, efficient scheduling of multi-channel high-speed packets is very necessary. In this case, the scheduling of multi-channel high-speed packets generally requires an a...

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Problems solved by technology

This makes the whole design process complicated, increases the design structure links, complicates the timing and functions, and increases the delay in some cases, thus complicating the circuit implementation process of the entire system, increasing the processing links, and increasing the delay. The difficulty increases, and the complexity of the entire chip design increases exponentially

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