Charge pump circuit suitable for low voltage operation

Abstract

The invention relates to a charge pump circuit, wherein each charge pump subunit is provided with four NMOS transistors and a pair of complementary two-phase clock signals, including: the drain of the first transistor is connected to the input terminal of the current stage, and the source The pole is connected to the output terminal of this stage; the drain of the second transistor is connected to the input terminal of this stage; the drain and gate of the third transistor are connected to the source of the second transistor together; the source of the third transistor is connected to At the gate of the first transistor; the drain and the gate of the fourth transistor are connected to the gate of the first transistor; the source of the fourth transistor is connected to the input terminal of this stage; the first phase clock signal passes through the first The capacitor is connected to the output terminal of the current stage; the first-phase clock signal is also connected to the second source of the second transistor through the third capacitor; the second-phase clock signal is connected to the gate of the first transistor through the second capacitor. The invention can increase the gate voltage of the NMOS transistor switch and reduce the side effect of the substrate bias effect.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a charge pump circuit used in an EEPROM or a flash memory chip for generating high voltage. Background technique [0002] With the rise of handheld devices and the Internet of Things, the demand for integrated circuit miniaturization and energy-saving design is becoming more and more urgent, which puts forward requirements for the design of low power supply voltage of semiconductor integrated circuits. Because EEPROM and flash memory devices have the characteristics of flexible data rewriting, stored data content will not be lost after power failure, and can be kept for a long time, they are more and more widely used in the system. [0003] In CMOS EEPROM or flash memory devices, whether based on floating gate technology or charge trap technology, a high voltage generation circuit is usually required to provide the high voltage required for programming and erasing operations....

AI Technical Summary

Problems solved by technology

The timing of the four-phase clock needs to be carefully adjusted, and it is sensitive to deviations in process and voltage. The circuit implementation is relatively complicated, and the clock overlap area for charging Cb will occupy the overall charge transfer time, making the effective turn-on time of M0 shorten

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