Simple Charge Pump Circuit for Low Voltage Operation

Abstract

The invention relates to a simple charge pump circuit suitable for low voltage operation. The simple charge pump circuit comprises a plurality of cascaded charge pump subunits; each level of charge pump subunit is provided with three NMOS (N-channel metal oxide semiconductor) transistors and a pair of two-phase clock signals. Each level of charge pump subunit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first-phase clock signal and a second-phase clock signal, wherein the first NMOS transistor serves as a transmission switch, the drain electrode of the first NMOS transistor is connected with the input end of the level of charge pump subunit, and the source electrode of the first NMOS transistor is connected with the output end of the level of charge pump subunit; the drain electrode and the grid electrode of the NMOS transistor are connected with each other and are connected to the output end of the level of charge pump subunit, and the source electrode is connected with the grid electrode of the first NMOS transistor; the drain electrode and the grid electrode of the third NMOS transistor are connected with each other and are connected to the grid electrode of the first NMOS transistor, and the source electrode is connected with the input end of the level of charge pump subunit; the first-phase clock signal is connected with the output end of the level of charge pump subunit through a first capacitor, and the second-phase clock signal is connected with the grid electrode of the first NMOS transistor through a second capacitor. The simple charge pump circuit suitable for low voltage operation improves the voltage of the grid electrodes of the NMOS transistors serving as the transmission switches with a simple structure, reduces the side effect of the substrate bias effect and simplifies the circuit board diagram design.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a charge pump circuit for generating high voltage in an EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory) or a flash memory chip. Background technique [0002] With the rise of handheld devices and the Internet of Things, the demand for integrated circuit miniaturization and energy-saving design is becoming more and more urgent, which puts forward requirements for the design of low power supply voltage of semiconductor integrated circuits. Because EEPROM and flash memory devices have the characteristics of flexible data rewriting, stored data content will not be lost after power failure, and can be kept for a long time, they are more and more widely used in the system. [0003] In CMOS EEPROM or flash memory devices, whether based on floating gate technology or charge trap technology, a high voltage generation ci...

AI Technical Summary

Problems solved by technology

The timing of the four-phase clock needs to be carefully adjusted, and it is sensitive to deviations in process and voltage. The circuit implementation is relatively complicated, and the clock overlap area for charging the capacitor Cb will occupy the overall charge transfer time, so that M0 can be effectively turned on. shortened time

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