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62results about How to "Reduce reverse current" patented technology

Charge pump circuit suitable for low voltage operation

ActiveCN104811033AAvoiding Parasitic Bipolar Transistor EffectsGood continuityApparatus without intermediate ac conversionLow voltageEngineering
The invention relates to a charge pump circuit, wherein each level charge pump subunit is provided with four NMOS (N-channel metal oxide semiconductor) transistors and a pair of phase complementary two-phase clock signals. The charge pump circuit suitable for low voltage operation is characterized in that a drain electrode of the first transistor is connected to the input end of the level of charge pump subunit, and a source electrode is connected to the output end of level of charge pump subunit; a drain electrode of the second transistor is connected to the input end of the level of charge pump subunit; a drain electrode and a grid electrode of the third transistor are connected to the source electrode of the second transistor; a source electrode of the third transistor is connected with the grid electrode of the first transistor; a drain electrode and a grid electrode of the fourth transistor are connected to the grid electrode of the first transistor; the source electrode of the fourth transistor is connected to the input end of the level of charge pump subunit; the first-phase clock signal is connected to the output end of the level of charge pump subunit through a first capacitor and is connected to a second source electrode of the second transistor through a third capacitor; the second-phase clock signal is connected to the grid electrode of the first transistor through a second capacitor. The charge pump circuit suitable for low voltage operation can improve the voltage of the grid electrodes of NMOS transistor switches and reduce the side effect of the substrate bias effect.
Owner:GIANTEC SEMICON LTD

Antenna and mobile terminal

The invention provides an antenna and a mobile terminal. The antenna comprises a first sub-antenna and a second sub-antenna, and radiators of the first sub-antenna and the second sub-antenna share a first branch, and the radiators of the first sub-antenna and the second sub-antenna further comprise a second branch. At setting, the second branch is electrically connected with the first branch, thesecond branch and the first branch are intersected at a set angle, and the ratio of the length of the second branch to the wavelength of a specific working frequency is within a set threshold value, wherein the specific working frequency is within the working frequency band of the second sub-antenna. The second branch is arranged to be electrically connected with the first branch and intersect with the first branch at the set angle, at the same time, the length of the second branch is limited, so that the resonance formed by the second branch is compatible with a half mode of the first branch,the frequency band width of the antenna is broadened. Moreover, a reverse current between the first branch and the second branch can be reduced, an efficiency pit is shallow, and further the performance of the antenna is improved, and the communication effect of the antenna is improved.
Owner:HUAWEI TECH CO LTD

High-voltage output converter

The invention provides a high-voltage output converter which uses a positive flyback circuit and comprises an input positive end, an input negative end, a transformer TX1, an MOS transistor Q1, an MOStransistor Q2, a diode D1, a diode D2, a diode D3, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an output positive end and an output negative end. According to the connection relation, the input positive end, the dotted terminal of the primary winding of the transformer TX1, the drain electrode of the MOS transistor Q1 and the input negative end are connected in sequence; the capacitor C2 and the MOS transistor Q2 are connected in series and then are connected in parallel to two ends of the primary winding; the synonym end of the secondary winding of the transformer TX1, the diodes D1 and D3 and the output positive end are connected in series; the output negative end, the diode D2 and the dotted terminal of the secondary winding of the transformer TX1 are sequentially connected in series; the capacitor C1 is connected in parallel between the cathode of the diode D1 and the dotted terminal of the secondary winding of the transformer TX1, the capacitor C2 is connectedin parallel between the synonym terminal of the secondary winding of the transformer TX1 and the anode of the diode D2, and the capacitor C3 is connected in parallel between the output positive terminal and the output negative terminal. High-voltage output can be realized, and main power is ensured to realize ZVS in a full-load range.
Owner:MORNSUN GUANGZHOU SCI & TECH

Self-biased differential drive rectifier circuit with wide dynamic range

The invention discloses a self-biased differential drive rectifier circuit with a wide dynamic range. The differential drive rectifier circuit is composed of a differential drive rectifier composed ofa first NMOS transistor (M1), a second NMOS transistor (M2), a first PMOS transistor (M3) and a second PMOS transistor (M4), and a diode of a special structure composed of a first diode (D1) and a second diode (D2). Input signals are RF+ and RF- and are connected with the input end of the differential drive rectifier through the first capacitor (C1) and the second capacitor (C2), the output end of the differential drive rectifier is connected with the first diode (D1) and the second diode (D2) which are connected in parallel, and the output ends of the first diode (D1) and the second diode (D2) are output signals Vout. Feedback is introduced from an output port through a diode, so that bias is provided for a grid electrode of an output PMOS of the differential drive rectifier, and the grid voltage of the differential drive rectifier is controlled. Under the condition of high input power, the reverse current of the differential drive rectifier is effectively reduced, and the dynamic range of high-efficiency output of the differential drive rectifier circuit is widened.
Owner:SOUTHEAST UNIV

Display device and display panel driver using grayscale voltages which correspond to grayscales

InactiveCN101169915BImproved PSRR (Power Supply Rejection Ratio) characteristicsStable outputStatic indicating devicesApparatus without intermediate ac conversionDriver circuitAudio power amplifier
A display device includes: a display panel (1); at least one data-line driver (2); and a plurality of operational amplifiers (26 1 to 26 m-1). The plurality of operational amplifiers is integrated in any of the at least one data-line driver and generates a plurality of reference voltages, respectively. The data-line driver includes: a driving circuit, a maximum grayscale voltage wiring, and a resistance ladder. The driving circuit drives the display panel. The maximum grayscale voltage wiring receives a maximum reference voltage in the plurality of reference voltages from a first operational amplifier in the plurality of operational amplifiers and supplies the maximum reference voltage to the driving circuit as a maximum grayscale voltage. The resistance ladder receives the plurality of reference voltages except the maximum reference voltage from the plurality of operational amplifiers except the first operational amplifier, respectively, and generates a plurality of grayscale voltages lower than the maximum grayscale voltage. The driving circuit (24, 25) drives data lines of the display panel (1) by using the maximum grayscale voltage and the plurality of grayscale voltages. The maximum grayscale voltage wiring (27) is isolated from the resistance ladder (28).
Owner:RENESAS ELECTRONICS CORP

Charge pump circuit suitable for low voltage operation

ActiveCN104811033BAvoiding Parasitic Bipolar Transistor EffectsGood continuityApparatus without intermediate ac conversionLow voltageEngineering
The invention relates to a charge pump circuit, wherein each charge pump subunit is provided with four NMOS transistors and a pair of complementary two-phase clock signals, including: the drain of the first transistor is connected to the input terminal of the current stage, and the source The pole is connected to the output terminal of this stage; the drain of the second transistor is connected to the input terminal of this stage; the drain and gate of the third transistor are connected to the source of the second transistor together; the source of the third transistor is connected to At the gate of the first transistor; the drain and the gate of the fourth transistor are connected to the gate of the first transistor; the source of the fourth transistor is connected to the input terminal of this stage; the first phase clock signal passes through the first The capacitor is connected to the output terminal of the current stage; the first-phase clock signal is also connected to the second source of the second transistor through the third capacitor; the second-phase clock signal is connected to the gate of the first transistor through the second capacitor. The invention can increase the gate voltage of the NMOS transistor switch and reduce the side effect of the substrate bias effect.
Owner:GIANTEC SEMICON LTD
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