Charge pump circuit suitable for low voltage operation

Abstract

The invention relates to a charge pump circuit, wherein each level charge pump subunit is provided with four NMOS (N-channel metal oxide semiconductor) transistors and a pair of phase complementary two-phase clock signals. The charge pump circuit suitable for low voltage operation is characterized in that a drain electrode of the first transistor is connected to the input end of the level of charge pump subunit, and a source electrode is connected to the output end of level of charge pump subunit; a drain electrode of the second transistor is connected to the input end of the level of charge pump subunit; a drain electrode and a grid electrode of the third transistor are connected to the source electrode of the second transistor; a source electrode of the third transistor is connected with the grid electrode of the first transistor; a drain electrode and a grid electrode of the fourth transistor are connected to the grid electrode of the first transistor; the source electrode of the fourth transistor is connected to the input end of the level of charge pump subunit; the first-phase clock signal is connected to the output end of the level of charge pump subunit through a first capacitor and is connected to a second source electrode of the second transistor through a third capacitor; the second-phase clock signal is connected to the grid electrode of the first transistor through a second capacitor. The charge pump circuit suitable for low voltage operation can improve the voltage of the grid electrodes of NMOS transistor switches and reduce the side effect of the substrate bias effect.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a charge pump circuit used in an EEPROM or a flash memory chip for generating high voltage. Background technique [0002] With the rise of handheld devices and the Internet of Things, the demand for integrated circuit miniaturization and energy-saving design is becoming more and more urgent, which puts forward requirements for the design of low power supply voltage of semiconductor integrated circuits. Because EEPROM and flash memory devices have the characteristics of flexible data rewriting, stored data content will not be lost after power failure, and can be kept for a long time, they are more and more widely used in the system. [0003] In CMOS EEPROM or flash memory devices, whether based on floating gate technology or charge trap technology, a high voltage generation circuit is usually required to provide the high voltage required for programming and erasing operations....

AI Technical Summary

Problems solved by technology

The timing of the four-phase clock needs to be carefully adjusted, and it is sensitive to deviations in process and voltage. The circuit implementation is relatively complicated, and the clock overlap area for charging Cb will occupy the overall charge transfer time, making the effective turn-on time of M0 shorten

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