Preparation method of gate oxide layer

Abstract

The invention discloses a preparation method of a grid oxide layer. The preparation method comprises the steps that: a part of materials on the surface of a part of STI is removed so that the side surface of an AA region is exposed out of the surface of the STI, an included angle between the side surface of the AA region and the surface of the STI is formed at a joint of the AA region and the STI, during the process of growing the grid oxide layer in the AA region, the grid oxide layer grows outwardly along the side surface of the AA region and the surface of the STI at the joint of the AA region and the STI and further fills a space between the surface of the STI and the side surface of the AA region, thereby increasing the thickness of the grid oxide layer growing at the joint of the AA region and the STI, reducing the thickness difference between a grid oxide layer growing on the surface of the AA region and the grid oxide layer growing at the joint of the AA region and the STI, eliminating a concave structure existing in the prior art, increasing breakdown voltage of the grid oxide layer growing at the joint of the AA region and the STI, and avoiding failure of HV GOI Vramp.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a method for preparing a grid oxide layer. Background technique [0002] The manufacturing process of MOSFET (Metallic Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) semiconductor device is to implant STI (Shallow Trench Isolation, shallow trench isolation) in a semiconductor substrate (such as a silicon substrate) between STIs Various semiconductor devices such as NMOS (N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor), PMOS (P-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor) are manufactured in the substrate area. [0003] The function of STI is to isolate each semiconductor device and prevent leakage current between devices. After the STI is formed, when manufacturing devices such as NMOS and PMOS, it is necessary to grow a gate oxide layer (Gate Oxide) on the surface of the substrate. [0004]...

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Problems solved by technology

Figure 4 The recessed structure of the gate oxide layer 5 in the dotted line box will result in the breakdown voltage (V bd ) is lower than the gate oxide layer 5 grown on the surface of the AA region, which in turn leads to the failure of the HV GOI VRamp (High Voltage GateOxide Integrity Voltage Ramp, high voltage gate oxide integrity ramp voltage test) test

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