Semiconductor device package

Abstract

A semiconductor device package includes a substrate, a transistor and a lead frame. Transistors are placed on the substrate. The transistor includes an active layer, at least one source, at least one drain, at least one gate, a first insulating layer, a first source pad, a first drain pad, at least one source plug and at least one drain plug stuffed. Both the source and the drain are located on the active layer. Orthographic projections of the source and the drain on the active layer form a source region and a drain region respectively. The first insulating layer covers at least part of the source and part of the drain. The first source pad is located on the first insulating layer, and the orthographic projection of the first source pad on the active layer forms a source pad region. The source pad region at least partially overlaps the drain region. The first drain pad is on the first insulating layer. The lead frame is placed on the side of the substrate opposite to the transistor, and is electrically connected to the gate.

Description

technical field [0001] The present invention relates to a semiconductor device package. Background technique [0002] A field effect transistor (Field Effect Transistor) is a switching element that uses the electric field effect in a material to control a current, and is widely used in circuits of semiconductor elements. Specifically, the field effect transistor includes a gate, a source, a drain and an active layer, and the source and the drain are respectively located on opposite sides of the active layer. By controlling the voltage of the gate to affect the electric field of the active layer, a current can be conducted between the source and the drain to be in an on state. [0003] Generally speaking, in order to be electrically connected with other elements, the field effect transistor may further include a source pad and a drain pad, which are respectively electrically connected to the source and the drain. The source pad and the drain pad usually have a large solderi...

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Problems solved by technology

[0004] On the other hand, in the packaging structure of the field effect transistor, poor packaging form will increase the parasitic capacitance of the field effect transistor, but will reduce the efficiency of the field effect transistor itself.

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