Formation method of semiconductor structure

Abstract

A formation method of a semiconductor structure comprises the steps of providing a semiconductor substrate, wherein a plurality of grid structures are formed on the semiconductor substrate, first openings are formed between the adjacent grid structures, source/drain regions are formed at the two sides of the grid structures, and etching stop layers are arranged on the surfaces of the grid structures; forming first dielectric layers in the first openings, wherein the surfaces of the first dielectric layers are lower than the top surfaces of the grid structures; forming size adjusting material layers covering the surfaces of the first dielectric layers and the grid structures; using a markless etching technology to etch the size adjusting material layers, and forming size adjusting side walls on the surfaces of the side walls of the etching stop layers; forming second dielectric layers covering the grid structures and the size adjusting side walls; etching the second dielectric layers, and forming second openings in the second dielectric layers, wherein the second openings expose out of the size adjusting side walls; etching the first dielectric layers in the first openings and the etching stop layers to form third openings. By forming the size adjusting side walls, a photoetching technology window is enlarged, and a bridging phenomenon is prevented.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a MOS transistor, including: providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, the gate structure including a gate dielectric layer and a gate electrode located on the gate dielectric layer ; forming offset sidewalls on the sidewall surfaces on both sides of the gate structure; using the gate structure and the offset sidewalls as a mask, performing shallow dopant ion implantation, and semiconductor substrates on both ...

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Problems solved by technology

[0004] However, the performance of MOS transistors f...

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