Charge transfer type sense amplifier

Abstract

The invention discloses a charge transfer type sense amplifier. The charge transfer type sense amplifier comprises a pre-charging unit and a bit line adjusting unit, wherein the pre-charging unit is used for electrifying a column data line node; the bit line adjusting unit is connected between an output end of the pre-charging unit and a bit line node of a memory unit; a bit line capacitor is connected between the bit line node and the ground, the bit line adjusting unit is used for providing a switch to ensure that the bit line node is connected with the column data line node and the charging of the bit line capacitor is realized when the bit line is pre-electrified; a control end of the bit line adjusting unit is connected with a supply voltage and connected with a second control signal through a second capacitor; the supply voltage is used for ensuring that the switch which connects the bit line node and the column data line node is in an on-state; and at the starting time of the pre-electrification of the bit line, the second control signal provides a level switching signal and is coupled to the control end of the bit line adjusting unit through the second capacitor to ensure that the voltage of the control end changes to increase the current of the switch and then the charging speed of the bit line capacitor is improved. The charge transfer type sense amplifier provided by the invention is capable of improving the charging speed and improving the circuit performance.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a charge transfer type sensitive amplifier. Background technique [0002] Such as figure 1 Shown is the circuit diagram of the existing charge transfer type sense amplifier; the existing charge transfer type sense amplifier includes: [0003] The gate of the NMOS transistor m101 is connected to the power supply voltage Vpwr, and remains on; the source is connected to the bit line node Bl101, and the capacitor Cbl101 is connected between the bit line node Bl101 and the ground, and the current Icell of the memory cell is connected through the bit line node Bl101. [0004] The source of the PMOS transistor p101 is connected to the power supply voltage, the drain is connected to the drain of the NMOS transistor m101 and both are connected to the column data line node Cl101, and the gate of the PMOS transistor p101 is connected to the precharge control signal Vpreb. [0005] The...

AI Technical Summary

Problems solved by technology

The voltage value of Cl1 is determined by charging the bit line capacitor Cbl from the power supply voltage through the PMOS transistor p101 and NMOS transistor n101. If Cl1 is kept greater than Vref during the comparison in the latch phase, the bit line capacitor Cbl must be charged with enough electricity. If the charging speed of the bit line capacitance Cbl is fast, the working speed of the charge transfer type sense amplifier will be faster; on the contrary, if the charging speed of the bit line capacitance Cbl remains unchanged and the operating speed of the charge transfer type sense amplifier is increased, the bit line Capacitor Cbl will not be able to charge enough charge to make voltage Cl1 greater than Vref, which will make subsequent reading failure

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