A high reliability parameter configuration method based on asic

Abstract

A method for high-reliability parameter configuration based on an application specific integrated circuit (ASIC) comprises a step S1 of configuring a hardware structure according to an ASIC method; a step S2 of reinforcing chip configuration parameters; a step S3 of storing to-be-configured parameters in a programmable read-only memory (PROM) positioned on the outer portion of a system chip; a step S4 of starting a parameter configuration module after the system chip is electrified; a step S5 of reading configuration parameter data stored in the PROM positioned on the outer portion of the system chip; a step S6 of performing data reliability selection on the read configuration data; a step S7 of identifying identification identifiers of configuration parameters of each module according to read parameters, performing decomposition and framing on parameter data of each module, and configuring the parameters to each function module; a step S8 of finishing initial configuration; a step S9 of starting real-time detection of the configuration parameters; a step S10 of detecting whether current system running parameters are normal according to set time, waiting for next-time detection if the current system running parameters are normal; and if there are errors, configuring the parameters again. The method has the advantages of easiness in implementation and reliability in parameter configuration and the like.

Description

technical field [0001] The invention mainly relates to the technical field of electronic system reliability reinforcement, in particular to an ASIC-based method for configuring high-reliability parameters. Background technique [0002] With the continuous improvement of the requirements of space exploration missions, the functional requirements of space electronic systems are getting higher and higher. In order to complete complex aerospace exploration tasks, large-scale integrated circuit chips represented by FPGA (Field Programmable Gate Array) have been widely used in electronic systems. Due to the single event effect caused by the space radiation environment, the logic state of the integrated circuit can be reversed, the instantaneous abnormality or interruption of the logic function, and with the decline of the CMOS (Complementary Metal Oxide Semiconductors) process, the threshold voltage of the PN junction is reduced, such as FPGA, processing Large-scale integrated ci...

AI Technical Summary

Problems solved by technology

Due to the single event effect caused by the space radiation environment, the logic state of the integrated circuit can be reversed, the instantaneous abnormality or interruption of the logic function, and with the decline of the CMOS (Complementary Metal Oxide Semiconductors) process, the threshold voltage of the PN junction is reduced, such as FPGA, processing Large-scale integrated circuits such as devices are increasingly threatened by single event effects, but there is currently no way to completely avoid the impact of single event effects on the normal operation of integrated circuits through chip design

Images