Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Junction-free field effect transistor and formation method thereof

A junction field effect, transistor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of high contact resistance, difficulty, increased difficulty in doping process, etc., to the extent that the interface scattering problem is reduced, The effect of simplifying the difficulty

Inactive Publication Date: 2016-01-13
SEMICON MFG INT (SHANGHAI) CORP
View PDF5 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, as the feature size decreases, the difficulty of the doping process increases, and as the difficulty of the doping process increases, it becomes more difficult to reduce the resistance between the source and drain regions through doping, while reducing the size of the gate It means that the size of the channel region is correspondingly smaller, which may exacerbate the short channel effect of MOSFET
[0006] In addition, since the source and drain regions of the MOSFET in the prior art are all doped semiconductor materials, when the conductive plugs connected to the source and drain regions are subsequently formed, there is a gap between the conductive plugs (usually metal materials) and the source and drain regions. There is a large contact resistance
[0007] Problems such as transistor leakage, large resistance between source and drain regions, and large contact resistance between conductive plugs and source and drain regions affect the performance of transistors

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Junction-free field effect transistor and formation method thereof
  • Junction-free field effect transistor and formation method thereof
  • Junction-free field effect transistor and formation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0061] Since the feature size of existing junctionless field effect transistors (such as MOSFETs) is gradually reduced, the difficulty of doping process for manufacturing MOSFETs is also gradually increasing.

[0062] At the same time, since the source and drain regions of existing MOSFETs are generally semiconductor materials, the resistance between the source and drain regions has been difficult to improve; and there is a large contact resistance between the semiconductor material and the conductive plug in the interconnection structure, generally Additional process steps are required to form a silicide contact layer on the source and drain regions to reduce contact resistance.

[0063] In addition, when the MOSFET is in the working state, the phenomenon of surface scattering (surface scattering) of carriers in the channel region becomes more serious, and the surface scattering phenomenon will affect the working performance of the junctionless field effect transistor to a cer...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a junction-free field effect transistor and a formation method thereof. The formation method comprises the steps of providing a substrate with a first region and a second region; forming a first doped region and a second doped region; removing part of the substrate so as to form a first opening and a second opening; and filling with openings with a metal containing material layer so as to form a source region and a drain region in the first opening and the second opening respectively. The invention further provides a junction-free field effect transistor, which comprises a substrate, a first doped region, a second doped region, a first gate structure, a second gate structure, a first opening and a second opening, and is characterized in that the first opening and the second opening are internally provided with metal containing material layers which act as a source region and a drain region respectively. The beneficial effects of the invention lie in that contact resistance between the source / drain region and a conductive plug is small, turn-on current is increased, and the performance of the junction-free field effect transistor is improved; and the difficulty of a doping process is simplified, and the degree of an interface scattering problem possibly occurred in the doped regions is reduced to a certain extent.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a junctionless field effect transistor and a forming method thereof. Background technique [0002] Metal-Oxide Semiconductor Field Effect Transistor (MetalOxideSemiconductorFieldEffectTransistor, MOSFET) in addition to the source and drain regions, the gate, there are also channel junctions such as PN junctions, heterojunctions, etc. in the channel region between the source and drain regions (junction). [0003] As the feature size of MOSFETs gradually decreases, more and more problems begin to emerge. For example, as the size of the MOSFET decreases, the degree of leakage of the MOSFET during operation increases. [0004] In addition, in order to further improve the performance of the MOSFET, it is also one of the more critical issues to minimize the resistance between the source and drain regions. In general, reducing the size of the gate or adjusting the doping le...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/78H01L29/45
Inventor 肖德元
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products