PMOS structure and formation method thereof

Abstract

The invention provides a PMOS structure and a formation method thereof. The formation method of the PMOS structure includes: a semiconductor substrate is provided, and a grid electrode structure and side walls positioned on sidewalls of two sides of the grid electrode structure are formed on the surface of the semiconductor substrate; the grid electrode structure and the side walls are regarded as masks, and grooves are formed at two sides of the side walls in the semiconductor substrate; germanium silicon seeding layers are formed on the surfaces of the bottom surfaces and side surfaces of the grooves, and the germanium silicon seeding layers are doped with fluorinions; and silicon germanium body layers are formed on the silicon germanium seeding layers, and remaining portions of the grooves are filled with the silicon germanium body layers. The fluorinions and silicon have strong bonding force, the germanium silicon seeding layers are doped with the fluorinions so that the transferred electron effect can be reduced, and the diffusion of P-type ions is prevented; besides, through the doping of the fluorinions, the stability of the device can be improved, and the negative bias temperature instability and the hot carrier injection effect are improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a PMOS structure and a forming method thereof. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are constantly decreasing, and the geometric dimensions of devices are also shrinking continuously following Moore's law. When the size of the semiconductor device is reduced to a certain extent, various problems caused by the semiconductor device approaching the physical limit appear one after another. The conventional source-drain region structure has been unable to meet the increasingly high requirements for device operation speed, so Embedded SiGe technology (EmbeddedSiGetechnology) to improve the electrical performance of PMOS has emerged. This technology embeds a silicon germanium layer in the substrate of the PMOS source and drain regions, and uses the stress generated by the latt...

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Problems solved by technology

[0005] The problem to be solved by the present invention is that when the embedded silicon germanium layer of PMOS structure is formed, the in-situ doped boron ion diffuses into the channel to cause the PMOS gate current to increase and the electrical performance to decrease, and the embedded silicon germanium layer Diffusion of germanium ions leads to deterioration of hot carrier injection effect and negative bias temperature instability, resulting in a decrease in device stability

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