Compound semiconductor device and method for controlling same
A control method and semiconductor technology, which is applied in the direction of semiconductor devices, transistors, electrical components, etc., can solve the problems of low threshold voltage, difficulty in practical application, inability to use gate drive circuits, etc., and achieve the effect of saving space
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Embodiment approach 1
[0035] image 3 It is a circuit diagram showing a schematic configuration of the compound semiconductor device of the present embodiment.
[0036] The composite semiconductor device 10 includes a GaN device (first field effect transistor) 1 and a Si-FET (second field effect transistor) 2 . Si-FET2 incorporates body diode 2d parasitic on Si-FET2.
[0037] The drain of GaN device 1 is connected to the high level side of power supply 3 . The source of the GaN device 1 is connected to the drain of the Si-FET 2 . The source of the Si-FET 2 is connected to the low-level side of the power supply 3 . That is, the composite semiconductor device 10 is formed by cascode-connecting (serially connecting) the GaN device 1 and the Si-FET 2 .
[0038] GaN device 1 includes Group III nitride semiconductors (compound semiconductors) typified by GaN, AlGaN, InGaN, and the like. Thus, the GaN device 1 as a normally-on field effect transistor can be realized. Also, a GaN device 1 with high w...
Embodiment approach 2
[0054] Figure 4 It is a timing chart comparing the waveform of the control signal applied to the gate of the GaN device and the waveform of the control signal applied to the gate of the Si-FET in this embodiment.
[0055] Here, a specific method of making the timing of turning on the Si-FET 2 earlier than the timing of turning on of the GaN device will be described. In addition, a specific method of making the timing of the GaN device non-conductive earlier than the timing of the Si-FET 2 non-conductive will be described here.
[0056] The control signal applied to the gate of GaN device 1 is delayed. At this time, for example, the timing at which the control signal applied to the gate of the GaN device 1 starts to rise is when the control signal applied to the gate of the Si-FET2 exceeds the operating threshold voltage Si-FET-Vth of the Si-FET2. time. The delay time is Figure 4 where is the delay time A. As a method of delaying the control signal applied to the gate of...
Embodiment approach 3
[0067] The composite semiconductor device of the present embodiment is the same as the above-mentioned respective embodiments except that the Si-FET 2 of the vertical structure is used. Si-FET2 has a first main surface and a second main surface. A gate electrode having a gate potential and a drain electrode having a drain potential are formed on the first main surface. A source electrode having a source potential is formed on the second main surface.
[0068] The GaN device 1 has a lateral structure as described above, and a gate electrode, a source electrode and a drain electrode are all formed on the first main surface. Therefore, no electrodes are formed on the second main surface of GaN device 1 .
[0069] refer to Figure 5 to Figure 7 A specific structure of the compound semiconductor device 100 as the compound semiconductor device of the present embodiment will be described. Figure 5 and Image 6 It is a plan view and a side view of the composite semiconductor dev...
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