Semiconductor device and manufacturing method for reducing surface topology and character line stringer residual

Abstract

The invention relates to a semiconductor device and a manufacturing method for reducing surface topology and character line stringer residual. According to the method, a substantially flat substrate for subsequent character line formation is prepared by forming a first dielectric filler material in an embedded oxide region and removing the dielectric filler material. The method takes into consideration the production of a semiconductor memory device of which the size is reduced as the character line stringer residual material is reduced.

Description

technical field [0001] The present invention relates to a structure of a semiconductor device and a method of forming the semiconductor device, and more particularly to an improved memory device and a method of manufacturing such a memory device. Background technique [0002] Flash memory devices generally include an array of memory cells arranged in columns and columns. Each memory cell includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. The gate corresponds to the word line, and the drain or source corresponds to the bit line of the memory array. The gate of a traditional flash memory cell is generally a double gate structure. The double gate structure includes a control gate and a floating gate, wherein the floating gate is sandwiched between two dielectric layers. space to capture carriers (such as electrons) to program memory cells. [0003] The semiconductor industry is increasingly moving towards...

AI Technical Summary

Problems solved by technology

These "stringers" become more of a problem when the size of wordlines and / or the space between those wordlines is reduced

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